Datasheet

2
Pinout
CD54HC40103
(CERDIP)
CD74HC40103, CD74HCT40103
(PDIP, SOIC)
TOP VIEW
Functional Diagram
TRUTH TABLE
CONTROL INPUTS
PRESET MODE ACTIONMR PL PE TE
1111 Synchronous Inhibit Counter
1110 Count Down
1 1 0 X Preset On Next Positive Clock Transition
1 0 X X Asynchronously Preset Asychronously
0 X X X Clear to Maximum Count
1 = High Level.
0 = Low Level.
X = Don’t Care.
Clock connected to clock input.
Synchronous Operation: changes occur on negative-to-positive clock transitions.
Load Inputs: MSB = P7, LSB = P0.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CP
MR
TE
P0
P1
P2
GND
P3
V
CC
TC
P7
P6
P5
P4
PL (ASYNC)
PE (SYNC)
7
10
11
12
13
GND
4
5
6
P3
P4
P5
P6
P7
P0
P1
P2
CP
MR
PE
PL TE
V
CC
TC
15 9 3 1 2 16 8
14
CD54HC40103, CD74HC40103, CD74HCT40103