Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS181D

Features

• Buffered Inputs

• High Current Bus Driver Outputs

• Two Independent Three-State Enable Controls

• Typical Propagation Delay t

PLH

PHL

= 8ns at V

=5V,

= 15pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate

CMOS three-state buffers are general purpose high-speed

non-inverting and inverting buffers. They have high drive cur-

rent outputs which enable high speed operation even when

driving large bus capacitances. These circuits possess the low

power dissipation of CMOS circuitry, yet have speeds compara-

ble to low power Schottky TTL circuits. Both circuits are capable

of driving up to 15 low power Schottky inputs.

The ’HC367 and ’HCT367 are non-inverting buffers, whereas

the ’HC368 and CD74HCT368 are inverting buffers. These

devices have two output enables, one enable (OE1) controls 4

gates and the other (OE2) controls the remaining 2 gates.

The ’HCT367 and CD74HCT368 logic families are speed, func-

tion and pin compatible with the standard LS logic family.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC367F3A -55 to 125 16 Ld CERDIP

CD54HC368F3A -55 to 125 16 Ld CERDIP

CD54HCT367F3A -55 to 125 16 Ld CERDIP

CD74HC367E -55 to 125 16 Ld PDIP

CD74HC367M -55 to 125 16 Ld SOIC

CD74HC367MT -55 to 125 16 Ld SOIC

CD74HC367M96 -55 to 125 16 Ld SOIC

CD74HC368E -55 to 125 16 Ld PDIP

CD74HC368M -55 to 125 16 Ld SOIC

CD74HC368MT -55 to 125 16 Ld SOIC

CD74HC368M96 -55 to 125 16 Ld SOIC

CD74HCT367E -55 to 125 16 Ld PDIP

CD74HCT367M -55 to 125 16 Ld SOIC

CD74HCT367MT -55 to 125 16 Ld SOIC

CD74HCT367M96 -55 to 125 16 Ld SOIC

CD74HCT368E -55 to 125 16 Ld PDIP

CD74HCT368M -55 to 125 16 Ld SOIC

CD74HCT368MT -55 to 125 16 Ld SOIC

CD74HCT368M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

November 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC367, CD54/74HCT367,

CD54/74HC368, CD74HCT368

High-Speed CMOS Logic Hex Buffer/Line Driver,

Three-State Non-Inverting and Inverting

[ /Title

(CD74

HC367

D74

HCT36

CD74

HC368

D74

HCT36

/Sub-

ject

(High

Speed

Summary of content (18 pages)

PAGE 1
[ /Title (CD74 HC367 , CD74 HCT36 7, CD74 HC368 , CD74 HCT36 8) /Subject (High Speed CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 Data sheet acquired from Harris Semiconductor SCHS181D November 1997 - Revised October 2003 High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting Features Ordering Information • Buffered Inputs PART NUMBER • High Current Bus Driver Outputs TEMP.
PAGE 2
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 Pinouts CD54HC367, CD54HCT367 (CERDIP) CD74HC367, CD74HCT367 (PDIP, SOIC) TOP VIEW CD54HC368 (CERDIP) CD74HC368, CD74HCT368 (PDIP, SOIC) TOP VIEW OE1 1 16 VCC OE1 1 16 VCC 1A 2 15 OE2 1A 2 15 OE2 1Y 3 14 6A 1Y 3 14 6A 2A 4 13 6Y 2A 4 13 6Y 2Y 5 12 5A 2Y 5 12 5A 3A 6 11 5Y 3A 6 11 5Y 3Y 7 10 4A 3Y 7 10 4A GND 8 9 4Y GND 8 9 4Y Functional Diagrams HC367, HCT367 OE1 1A 1Y 2A 2Y HC368, CD74HCT368 1 16 2 15 3 14 4
PAGE 3
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 Logic Diagram VCC 16 ONE OF SIX IDENTICAL CIRCUITS 2 1A 3 (NOTE 1) 1Y GND 8 1 OE1 4 15 5 2A 2Y OE2 6 7 3A 3Y 10 4A 9 4Y 12 5A 11 5Y 14 6A 13 6Y NOTE: 1. Inverter not included in HC/HCT367 FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF THOSE SHOWN, i.e., 1Y, 2Y, ETC.
PAGE 4
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.
PAGE 6
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 Switching Specifications PARAMETER Propagation Delay, Data to Outputs HC/HCT368 Propagation Delay, Output Enable and Disable to Outputs Output Transition Time Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF tPLH, tPHL tTLH, tTHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 105 130 160 ns 4.
PAGE 7
CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368 Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH tPHL 6ns 10% 2.7 1.3 OUTPUT LOW TO OFF 90% OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 4. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC367M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT367M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT368M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC367M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT367M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT368M96 SOIC D 16 2500 333.2 345.9 28.
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.