Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Multivibrator Monostable 18 ns TSSOP 16

Data sheet acquired from Harris Semiconductor

SCHS166F

Features

• Overriding RESET Terminates Output Pulse

• Triggering from the Leading or Trailing Edge

• Q and

Q Buffered Outputs

• Separate Resets

• Wide Range of Output-Pulse Widths

• Schmitt Trigger on B Inputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Pinout

CD54HC221

(CERDIP)

CD74HC221

(PDIP, SOIC, SOP, TSSOP)

CD74HCT221

(PDIP, SOIC)

TOP VIEW

Description

The ’HC221 and CD74HCT221 are dual monostable

multivibrators with reset. An external resistor (R

) and an

external capacitor (C

) control the timing and the accuracy

for the circuit. Adjustment of R

and C

provides a wide

range of output pulse widths from the Q and

Q terminals.

Pulse triggering on the B input occurs at a particular voltage

level and is not related to the rise and fall time of the trigger

pulse.

Once triggered, the outputs are independent of further trigger

inputs on

A and B. The output pulse can be terminated by a

LOW level on the Reset (

R) pin. Trailing Edge triggering (A)

and leading-edge-triggering (B) inputs are provided for

triggering from either edge of the input pulse. On power up,

the IC is reset. If either Mono is not used each input (on the

unused device) must be terminated either high or low.

The minimum value of external resistance, R

, is typically 500Ω.

The minimum value of external capacitance, C

, is 0pF. The

calculation for the pulse width is t

= 0.7 R

at V

= 4.5V.

GND

Ordering Information

PART NUMBER TEMP. RANGE (

C) PACKAGE

CD54HC221F3A -55 to 125 16 Ld CERDIP

CD74HC221E -55 to 125 16 Ld PDIP

CD74HC221M -55 to 125 16 Ld SOIC

CD74HC221MT -55 to 125 16 Ld SOIC

CD74HC221M96 -55 to 125 16 Ld SOIC

CD74HC221NSR -55 to 125 16 Ld SOP

CD74HC221PW -55 to 125 16 Ld TSSOP

CD74HC221PWR -55 to 125 16 Ld TSSOP

CD74HC221PWT -55 to 125 16 Ld TSSOP

CD74HCT221E -55 to 125 16 Ld PDIP

CD74HCT221M -55 to 125 16 Ld SOIC

CD74HCT221MT -55 to 125 16 Ld SOIC

CD74HCT221M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

November 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC221, CD74HC221,

CD74HCT221

High-Speed CMOS Logic

Dual Monostable Multivibrator with Reset

[

/Title

(

CD74

C221

D74

CT22

)

Sub-

ect

(

High

peed

MOS

ogic

ual

onos

able

ulti-

Summary of content (24 pages)

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[ /Title (CD74 HC221 , CD74 HCT22 1) /Subject (High Speed CMOS Logic Dual Monos table Multi- CD54HC221, CD74HC221, CD74HCT221 Data sheet acquired from Harris Semiconductor SCHS166F High-Speed CMOS Logic Dual Monostable Multivibrator with Reset November 1997 - Revised October 2003 Features Description • Overriding RESET Terminates Output Pulse The ’HC221 and CD74HCT221 are dual monostable multivibrators with reset.
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CD54HC221, CD74HC221, CD74HCT221 Functional Diagram 1CX 1RX VCC 14 15 1CX 1CXRX 13 1Q 1A 1 MONO 1 4 1B 1Q 2 1R 2R 3 11 5 9 2Q 2A MONO 2 10 12 2B 2Q 2CX 2CXRX 6 7 VCC 2CX 2RX TRUTH TABLE INPUTS OUTPUTS A B R Q Q H X H L H X L H L H L ↑ H ↓ H H X X L L H L H ↑ (Note 3) (Note 3) H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low Level, = One High Level Pulse, = One Low Le
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CD54HC221, CD74HC221, CD74HCT221 Logic Diagram VCC 16 C P RX N A B 1 (9) R 3 (11) 2 (10) P VCC R D RESET FF S C Q R P OP AMP R2 RXCX C VCC MIRROR VOLTAGE QM 15 (7) + QM R3 PP CX R MASK FF S Q MAIN FF R1 R4 Q N VCC 14 (6) PULLDOWN FF D CX Q N 8 C 4 (12) C (13) 5 Q GND R Q Q + OP AMP 3
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CD54HC221, CD74HC221, CD74HCT221 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .
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CD54HC221, CD74HC221, CD74HCT221 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.
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CD54HC221, CD74HC221, CD74HCT221 Prerequisite For Switching Function (Continued) 25oC PARAMETER Input Pulse Width Reset -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tWL 2 70 - - 90 - 105 - ns 4.5 14 - - 18 - 21 - ns 6 12 - - 15 - 18 - ns 2 0 - - 0 - 0 - ns 4.5 0 - - 0 - 0 - ns Recovery Time R to A or B tSU 6 0 - - 0 - 0 - ns Output Pulse Width Q or Q CX = 0.
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CD54HC221, CD74HC221, CD74HCT221 Switching Specifications Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH CL = 50pF 2 - - 160 - 200 - 240 ns 4.5 - - 32 - 40 - 48 ns 6 - - 27 - 34 - 41 ns 2 - - 180 - 225 - 270 ns 4.5 - - 36 - 45 - 54 ns 6 - - 31 - 38 - 46 ns 2 - - 75 - 95 - 110 ns 4.
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CD54HC221, CD74HC221, CD74HCT221 Test Circuits and Waveforms tfCL trCL CLOCK tWL + tWH = 90% 10% I fCL CLOCK 50% 50% 1.3V 0.3V FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tf = 6ns tf = 6ns tr = 6ns VCC 90% 50% 10% GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. FIGURE 1.
PAGE 9
CD54HC221, CD74HC221, CD74HCT221 Typical Performance Curves RX = 10K RX = 10K VCC = 5V TA = 25oC 680 0.9 K FACTOR tW, PULSE WIDTH (µs) 685 CX = 1µF 675 670 HCT 0.8 0.7 665 -75 -50 -25 0 25 50 75 100 125 150 0.6 175 0 2 4 6 VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (oC) FIGURE 5. HC/HCT221 OUTPUT PULSE WIDTH vs TEMPERATURE 10 FIGURE 6. HC/HCT221 K FACTOR vs SUPPLY VOLTAGE 106 106 VCC = 4.
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CD54HC221, CD74HC221, CD74HCT221 10
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC221M96 Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC221NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC221PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC221M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC221NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC221PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC221PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT221M96 SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.