Datasheet

10
FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL)
FIGURE 8. CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD
NOTE: Illegal states in BCD counters corrected in one count. NOTE: Illegal states in BCD counters corrected in one or two counts.
FIGURE 9. ’HC192, ’HCT193 STATE DIAGRAMS
Test Circuits and Waveforms (Continued)
INPUT LEVEL
INPUT LEVEL
Q = p
V
S
t
H
t
SU
(L)
Q = p
Q
n
PL
Pn
t
SU
(H)
V
S
V
S
t
H
P0 P1 P2 P3
TCU
TCD
MR
Q
0
Q
1
Q
2
Q
3
CPU
CPD
PL
UP CLOCK
DOWN CLOCK
ASYNCHRONOUS,
PARALLEL LOAD
RESET
OUTPUT
CARRY
BORROW
DATA INPUT
P0 P1 P2 P3
TCU
TCD
MR
Q
0
Q
1
Q
2
Q
3
CPU
CPD
PL
234
5
6
7
89101112
13
14
15
10
COUNT UP
234
5
6
7
89101112
13
14
15
10
COUNT DOWN