Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Push pull SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS157C

Features

• Buffered Inputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

Pinout

CD54HC166, CD54HCT166

(CERDIP)

CD74HC166, CD74HCT166

(PDIP, SOIC)

TOP VIEW

Description

The ’HC166 and ’HCT166 8-bit shift register is fabricated

with silicon gate CMOS technology. It possesses the low

power consumption of standard CMOS integrated circuits,

and can operate at speeds comparable to the equivalent low

power Schottky device.

The ’HCT166 is functionally and pin compatible with the

standard ’LS166.

The 166 is an 8-bit shift register that has fully synchronous

serial or parallel data entry selected by an active LOW Parallel

Enable (

PE) input. When the PE is LOW one setup time before

the LOW-to-HIGH clock transition, parallel data is entered into

the register. When

PE is HIGH, data is entered into the internal

bit position Q0 from Serial Data Input (DS), and the remaining

bits are shifted one place to the right (Q0 → Q1 → Q2, etc.)

with each positive-going clock transition. For expansion of the

nected to the DS input of the succeeding stage.

The clock input is a gated OR structure which allows one

input to be used as an active LOW Clock Enable (

CE) input.

The pin assignment for the CP and

CE inputs is arbitrary and

can be reversed for layout convenience. The LOW-to-HIGH

transition of

CE input should only take place while the CP is

HIGH for predictable operation.

A LOW on the Master Reset (

MR) input overrides all other

inputs and clears the register asynchronously, forcing all bit

positions to a LOW state.

Ordering Information

GND

PART NUMBER TEMP. RANGE (

C) PACKAGE

CD54HC166F3A -55 to 125 16 Ld CERDIP

CD54HCT166F3A -55 to 125 16 Ld CERDIP

CD74HC166E -55 to 125 16 Ld PDIP

CD74HC166M -55 to 125 16 Ld SOIC

CD74HC166MT -55 to 125 16 Ld SOIC

CD74HC166M96 -55 to 125 16 Ld SOIC

CD74HCT166E -55 to 125 16 Ld PDIP

CD74HCT166M -55 to 125 16 Ld SOIC

CD74HCT166MT -55 to 125 16 Ld SOIC

CD74HCT166M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

February 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC166, CD74HC166,

CD54HCT166, CD74HCT166

High-Speed CMOS Logic

8-Bit Parallel-In/Serial-Out Shift Register

[

/Title

(

CD74

C166

D74

CT16

)

Sub-

ect

(

High

peed

MOS

ogic

-Bit

aral-

el-

n/Seri

Summary of content (16 pages)

PAGE 1
[ /Title (CD74 HC166 , CD74 HCT16 6) /Subject (High Speed CMOS Logic 8-Bit ParallelIn/Seri CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 Data sheet acquired from Harris Semiconductor SCHS157C February 1998 - Revised October 2003 High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register Features Description • Buffered Inputs The ’HC166 and ’HCT166 8-bit shift register is fabricated with silicon gate CMOS technology.
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CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 Functional Diagram D0 D1 D2 D3 D4 D5 D6 D7 PARALLEL ENABLE CIRCUIT PE D0 D7 DS 8 - REGISTERS Q7 CP CE MR TRUTH TABLE INPUTS INTERNAL Q STATES PARALLEL MASTER RESET PARALLEL ENABLE CLOCK ENABLE CLOCK SERIAL D0 D7 Q0 Q1 OUTPUT Q7 L X X X X X L L L H X L L X X Q00 Q10 Q0 H L L ↑ X a...
PAGE 3
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) ICC VCC or GND 0 High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 8 - 80 - 160 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL -0.
PAGE 5
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 Prerequisite For Switching Specifications (Continued) 25oC PARAMETER MR Pulse Width (Figure 1) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS tw 2 100 - 125 - 150 - ns 4.5 20 - 25 - 30 - ns 6 17 - 21 - 26 - ns 2 80 - 100 - 120 - ns 4.
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CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 Switching Specifications PARAMETER Output Transition Time (Figure 3) Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tTLH, tTHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns 2 - 160 200 240 ns 4.
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CD54HC166, CD74HC166, CD54HCT166, CD74HCT166 Test Circuits and Waveforms tr = 6ns (Continued) tf = 6ns 90% 50% 10% INPUT GND tTLH 90% INVERTING OUTPUT tPHL FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL VCC 90% GND tH(H) 3V 2.7V 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC166M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT166M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC166M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT166M96 SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.