Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Receiver, transceiver PDIP 20

Data sheet acquired from Harris Semiconductor

SCHS245B

Features

• Buffered Inputs

• Typical Propagation Delay

- 4ns at V

= 5V, T

= 25

C, C

= 50pF

• Exceeds 2kV ESD Protection per MIL-STD-883,

Method 3015

• SCR-Latchup-Resistant CMOS Process and Circuit

Design

• Speed of Bipolar FAST™/AS/S with Signiﬁcantly

Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and

Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Description

The ’AC245 and ’ACT245 are octal-bus transceivers that

utilize Advanced CMOS Logic technology. They are non-

inverting three-state bidirectional transceiver-buffers

intended for two-way transmission from “A” bus to “B” bus or

“B” bus to “A”. The logic level present on the direction input

(DIR) determines the data direction. When the output enable

input (

OE) is HIGH, the outputs are in the high-impedance

state.

Pinout

CD54AC245, CD54ACT245

(CERDIP)

CD74AC245, CD74ACT245

(PDIP, SOIC, SSOP)

TOP VIEW

Ordering Information

PART

NUMBER

TEMP.

RANGE (

C) PACKAGE

CD54AC245F3A -55 to 125 20 Ld CERDIP

CD74AC245E -55 to 125 20 Ld PDIP

CD74AC245M -55 to 125 20 Ld SOIC

CD74AC245SM -55 to 125 20 Ld SSOP

CD54ACT245F3A -55 to 125 20 Ld CERDIP

CD74ACT245E -55 to 125 20 Ld PDIP

CD74ACT245M -55 to 125 20 Ld SOIC

CD74ACT245SM -55 to 125 20 Ld SSOP

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all

electrical specifications. Please contact your local TI sales office or

customer service for ordering information.

DIR

GND

September 1998 - Revised October 2000

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

FAST™ is a Trademark of Fairchild Semiconductor.

CD54/74AC245,

CD54/74ACT245

Octal-Bus Transceiver,

Three-State, Non-Inverting

[ /Title

(CD74

AC245

CD74

ACT24

/Sub-

ject

(Octal-

Bus

Trans-

ceiver,

Three-

State,

Non-

Invert-

ing)

/Autho

r ()

/Key-

words

(Har-

ris

Semi-

con-

ductor,

Advan

ced

CMOS

,Harris

Semi-

con-

Summary of content (17 pages)

PAGE 1
CD54/74AC245, CD54/74ACT245 Data sheet acquired from Harris Semiconductor SCHS245B Octal-Bus Transceiver, Three-State, Non-Inverting September 1998 - Revised October 2000 Features Description • Buffered Inputs The ’AC245 and ’ACT245 are octal-bus transceivers that utilize Advanced CMOS Logic technology. They are noninverting three-state bidirectional transceiver-buffers intended for two-way transmission from “A” bus to “B” bus or “B” bus to “A”.
PAGE 2
CD54/74AC245, CD54/74ACT245 Functional Diagram A0 A1 A2 A3 A4 A5 A6 A7 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B0 B1 B2 B3 B4 B5 B6 B7 1 DIR 19 OE TRUTH TABLE CONTROL INPUTS OE DIR OPERATION L L B Data to A Bus L H A Data to B Bus H X Isolation H = High Level, L = Low Level, X = Irrelevant To prevent excess currents in the High-Z (isolation) modes, all I/O terminals should be terminated with 10kΩ to 1MΩ resistors.
PAGE 3
CD54/74AC245, CD54/74ACT245 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .
PAGE 4
CD54/74AC245, CD54/74ACT245 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.
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CD54/74AC245, CD54/74ACT245 ACT Input Load Table INPUT UNIT LOAD An, Bn 0.83 OE 0.64 DIR 0.25 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC PARAMETER -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 96 - - 106 ns 3.3 (Note 9) 3.2 - 10.8 3 - 11.9 ns 5 (Note 10) 2.2 - 7.7 2.1 - 8.5 ns 1.
PAGE 6
CD54/74AC245, CD54/74ACT245 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) (Continued) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS Three-State Output Capacitance CO - - 15 - - 15 - pF Input Capacitance CI - - - 10 - - 10 pF CPD (Note 11) - - 57 - - 57 - pF PARAMETER Power Dissipation Capacitance NOTES: 8. Limits tested 100% 9. 3.3V Min is at 3.6V, Max is at 3V. 10. 5V Min is at 5.5V, Max is at 4.5V. 11.
PAGE 7
CD54/74AC245, CD54/74ACT245 tf = 3ns tr = 3ns INPUT LEVEL 90% OUTPUTS DISABLED VS 10% tPLZ GND tPZL OUTPUT: LOW TO OFF TO LOW VS 0.2 VCC tPHZ VOL (≠ VCC) tPZH 0.8 VCC VS OUTPUT: HIGH TO OFF TO HIGH OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED GND (tPHZ, tPZH) OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE OPEN (tPHL, tPLH) 2 VCC (tPLZ, tPZL) RL 500Ω (OPEN DRAIN) OUT RL CL 500Ω 50pF (NOTE 14) DUT WITH THREESTATE OUTPUT NOTE: 14. For AC Series only: When VCC = 1.5V, RL = 1kΩ. FIGURE 2.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74AC245M96 Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74ACT245M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74ACT245SM96 SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC245M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74ACT245M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74ACT245SM96 SSOP DB 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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