Datasheet

CD54AC161, CD74AC161

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS239C – SEPTEMBER 1998 – REVISED MARCH 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

CLR

LOAD

ENT

ENP

CLK

RCO

†

For simplicity, routing of complementary signals LD

and CK is not shown on this overall logic diagram. The uses of these signals are shown

on the logic diagram of the D/T flip-flops.

, 2T/1C3

†