Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - multiplexers, demultiplexers SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS047G

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

CD4051B, CD4052B, CD4053B

Features

• Wide Range of Digital and Analog Signal Levels

- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V

- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20V

P-P

• Low ON Resistance, 125Ω (Typ) Over 15V

P-P

Signal Input

Range for V

-V

= 18V

• High OFF Resistance, Channel Leakage of ±100pA (Typ)

at V

-V

= 18V

• Logic-Level Conversion for Digital Addressing Signals of

3V to 20V (V

-V

= 3V to 20V) to Switch Analog

Signals to 20V

P-P

-V

= 20V)

• Matched Switch Characteristics, r

= 5Ω (Typ) for

-V

= 15V

• Very Low Quiescent Power Dissipation Under All Digital-

Control Input and Supply Conditions, 0.2µW (Typ) at

-V

= V

-V

= 10V

• Binary Address Decoding on Chip

• 5V, 10V, and 15V Parametric Ratings

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package

Temperature Range, 100nA at 18V and 25

• Break-Before-Make Switching Eliminates Channel

Overlap

Applications

• Analog and Digital Multiplexing and Demultiplexing

• A/D and D/A Conversion

• Signal Gating

CMOS Analog Multiplexers/Demultiplexers

with Logic Level Conversion

The CD4051B, CD4052B, and CD4053B analog multiplexers

are digitally-controlled analog switches having low ON

impedance and very low OFF leakage current. Control of

analog signals up to 20V

P-P

can be achieved by digital

signal amplitudes of 4.5V to 20V (if V

-V

= 3V, a

-V

of up to 13V can be controlled; for V

-V

level

differences above 13V, a V

-V

of at least 4.5V is

required). For example, if V

= +4.5V, V

= 0V, and

= -13.5V, analog signals from -13.5V to +4.5V can be

controlled by digital inputs of 0V to 5V. These multiplexer

circuits dissipate extremely low quiescent power over the

full V

-V

and V

-V

supply-voltage ranges,

independent of the logic state of the control signals. When

a logic “1” is present at the inhibit input terminal, all

channels are off.

The CD4051B is a single 8-Channel multiplexer having three

binary control inputs, A, B, and C, and an inhibit input. The

three binary signals select 1 of 8 channels to be turned on,

and connect one of the 8 inputs to the output.

The CD4052B is a differential 4-Channel multiplexer having

two binary control inputs, A and B, and an inhibit input. The

two binary input signals select 1 of 4 pairs of channels to be

turned on and connect the analog inputs to the outputs.

The CD4053B is a triple 2-Channel multiplexer having three

separate digital control inputs, A, B, and C, and an inhibit

input. Each control input selects one of a pair of channels

which are connected in a single-pole, double-throw

conﬁguration.

When these devices are used as demultiplexers, the

“CHANNEL IN/OUT” terminals are the outputs and the

“COMMON OUT/IN” terminals are the inputs.

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD4051BF3A, CD4052BF3A,

CD4053BF3A

-55 to 125 16 Ld CERAMIC

DIP

CD4051BE, CD4052BE,

CD4053BE

-55 to 125 16 Ld PDIP

CD4051BM, CD4051BMT,

CD4051BM96

CD4052BM, CD4052BMT,

CD4052BM96

CD4053BM, CD4053BMT,

CD4053BM96

-55 to 125 16 Ld SOIC

CD4051BNSR, CD4052BNSR,

CD4053BNSR

-55 to 125 16 Ld SOP

CD4051BPW, CD4051BPWR,

CD4052BPW, CD4052BPWR

CD4053BPW, CD4053BPWR

-55 to 125 16 Ld TSSOP

August 1998 - Revised October 2003

[ /Title

(CD405

1B,

CD4052

CD4053

/Sub-

ject

(CMOS

Analog

Multi-

plex-

ers/Dem

ultiplex-

ers with

Logic

Level

Conver-

sion)

/Author

()

/Key-

words

(Harris

Semi-

conduc-

tor,

CD4000

Summary of content (28 pages)

PAGE 1
CD4051B, CD4052B, CD4053B August 1998 - Revised October 2003 Data sheet acquired from Harris Semiconductor SCHS047G Features • Wide Range of Digital and Analog Signal Levels - Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V - Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 2
CD4051B, CD4052B, CD4053B Pinouts CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP) TOP VIEW 4 1 16 VDD 6 2 15 2 COM OUT/IN 3 14 1 7 4 13 0 CHANNELS IN/OUT CD4052B (PDIP, CDIP, SOP, TSSOP) TOP VIEW 0 1 16 VDD 2 2 15 2 COMMON “Y” OUT/IN 3 14 1 Y CHANNELS IN/OUT X CHANNELS IN/OUT CHANNELS IN/OUT CHANNELS IN/OUT Y CHANNELS IN/OUT 3 4 13 COMMON “X” OUT/IN 5 5 12 3 1 5 12 0 INH 6 11 A INH 6 11 3 VEE 7 10 B VEE 7 10 A VSS 8 9 C VSS 8 9 B X CHANNELS IN/OUT CD4053B (PDIP, CDIP, SOP, TSSOP
PAGE 3
CD4051B, CD4052B, CD4053B Functional Block Diagrams (Continued) CD4052B X CHANNELS IN/OUT 3 2 1 0 11 15 14 12 TG 16 VDD A † 10 B † 9 INH † 6 TG BINARY TO 1 OF 4 DECODER WITH INHIBIT LOGIC LEVEL CONVERSION TG COMMON X OUT/IN TG 13 TG TG 3 COMMON Y OUT/IN TG TG 8 VSS 7 VEE 1 5 2 4 0 1 2 3 Y CHANNELS IN/OUT CD4053B LOGIC LEVEL CONVERSION 16 VDD BINARY TO 1 OF 2 DECODERS WITH INHIBIT IN/OUT cy cx by bx ay ax 3 5 1 2 13 12 TG COMMON OUT/IN ax OR ay 14 A
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CD4051B, CD4052B, CD4053B TRUTH TABLES INPUT STATES INHIBIT C B A “ON” CHANNEL(S) 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 X X X None CD4051B CD4052B INHIBIT B A 0 0 0 0x, 0y 0 0 1 1x, 1y 0 1 0 2x, 2y 0 1 1 3x, 3y 1 X X None CD4053B INHIBIT A OR B OR C 0 0 ax or bx or cx 0 1 ay or by or cy 1 X None X = Don’t Care 4
PAGE 5
CD4051B, CD4052B, CD4053B Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-) Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA Package Thermal Impedance, θJA (see Note 1): E (PDIP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) package . . . . . . . . . . . . . . . . . .
PAGE 6
CD4051B, CD4052B, CD4053B Common Conditions Here: If Whole Table is For the Full Temp. Range, VSUPPLY = ±5V, AV = +1, RL = 100Ω, Unless Otherwise Specified (Continued) (Note 3) Electrical Specifications LIMITS AT INDICATED TEMPERATURES (oC) CONDITIONS 25 PARAMETER VIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 125 MIN TYP MAX UNITS 5 1.5 1.5 1.5 1.5 - - 1.5 V 10 3 3 3 3 - - 3 V 15 4 4 4 4 - - 4 V 5 3.5 3.5 3.5 3.5 3.
PAGE 7
CD4051B, CD4052B, CD4053B Electrical Specifications TEST CONDITIONS LIMITS PARAMETER VIS (V) VDD (V) RL (kΩ) TYP UNITS Total Harmonic Distortion, THD 2 (Note 3) 5 10 0.3 % 3 (Note 3) 10 0.2 % 5 (Note 3) 15 0.
PAGE 8
CD4051B, CD4052B, CD4053B Typical Performance Curves (Continued) 600 250 rON , CHANNEL ON RESISTANCE (Ω) rON , CHANNEL ON RESISTANCE (Ω) TA = 25oC VDD - VEE = 5V 500 400 300 200 10V 15V 100 0 -10 -7.5 -5 -2.5 0 2.5 5 7.5 VDD - VEE = 15V 200 TA = 125oC 150 TA = 25oC 100 TA = -55oC 50 0 -10 10 -7.5 -5 FIGURE 3.
PAGE 9
CD4051B, CD4052B, CD4053B Test Circuits and Waveforms VDD = 15V VDD = 7.5V VDD = 5V VDD = 5V 5V 7.5V 16 5V 16 16 16 VSS = 0V VSS = 0V VSS = 0V VEE = 0V 7 8 VEE = -7.5V 7 8 VEE = -10V 7 8 7 8 VEE = -5V VSS = 0V (D) (C) (B) (A) NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels are: “0” = VSS and “1” = VDD. The analog signal (through the TG) may swing from VEE to VDD. FIGURE 9.
PAGE 10
CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued) VDD 1 2 3 4 5 6 7 8 IDD VDD 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IDD VDD 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 CD4052 CD4051 16 15 14 13 12 11 10 9 IDD CD4053 FIGURE 13.
PAGE 11
CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued) VDD VDD 1 2 3 4 5 6 7 8 Ι 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Ι CD4051 CD4053 VDD 16 15 14 13 12 11 10 9 KEITHLEY 160 DIGITAL MULTIMETER TG “ON” 10kΩ X-Y PLOTTER FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT CIRCUIT VDD 1 2 3 4 5 6 7 8 VDD Ι VSS CD4051 CD4053 VSS X H.P. MOSELEY 7030A CD4052 VDD 16 15 14 13 12 11 10 9 Y VSS FIGURE 17.
PAGE 12
CD4051B, CD4052B, CD4053B Test Circuits and Waveforms (Continued) DIFFERENTIAL SIGNALS CD4052 CD4052 COMMUNICATIONS LINK DIFF. AMPLIFIER/ LINE DRIVER DIFF. MULTIPLEXING DIFF. RECEIVER DEMULTIPLEXING FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B Special Considerations In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load).
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4051BM96G3 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.0 Q1 CD4051BM96G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4051BM96 SOIC D 16 2500 333.2 345.9 28.6 CD4051BM96G3 SOIC D 16 2500 364.0 364.0 27.0 CD4051BM96G4 SOIC D 16 2500 367.0 367.0 38.0 CD4051BM96G4 SOIC D 16 2500 333.2 345.9 28.6 CD4051BPWR TSSOP PW 16 2000 364.0 364.0 27.0 CD4051BPWRG4 TSSOP PW 16 2000 367.0 367.0 35.
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