Datasheet

3
CD4052B
CD4053B
Functional Block Diagrams (Continued)
1211 15 14
0123
3210
X CHANNELS IN/OUT
Y CHANNELS IN/OUT
BINARY
TO
1 OF 4
DECODER
WITH
INHIBIT
13
3
COMMON Y
OUT/IN
COMMON X
OUT/IN
78
16
6
9
10
A
†
B †
INH †
V
SS
V
EE
V
DD
TG
TG
TG
TG
TG
TG
TG
TG
4251
LOGIC
LEVEL
CONVERSION
11
10
9
6
A †
B †
C †
INH †
123 5 1 2 13
TG
TG
TG
TG
TG
TG
4
COMMON
OUT/IN
axaybxbycxcy
8
7
V
SS
V
EE
16
V
DD
IN/OUT
15
14
BINARY TO
1 OF 2
DECODERS
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
V
DD
†All inputs are protected by standard CMOS protection network.
COMMON
OUT/IN
COMMON
OUT/IN
ax OR ay
bx OR by
cx OR cy
CD4051B, CD4052B, CD4053B