Datasheet

CB2
VC1
VSS
CONV_H
AGND
VSS
TS1+
SCLK_S
VSSD
FAULT_S
DRDY_S
ALERT_S
VSS
CONV_S
NC30
TS1–
VREF
LDOA
SDI_S
CS_S
CB1
VC0
VSS
SDO_S
LDOD1
AUX
VC3
REG50
DRDY_H
ALERT_H
FAULT_H
SCLK_H
SDO_H
SDI_H
CB4
VC4 HSEL
VC5
CB6
DRDY_N
CONV_N SCLK_N
SDO_N
GPAI–
LDOD2
BAT1
NC62 NC51
TEST
CS_H
CB3
VC2
VC6
BAT2 TS2–
TS2+ SDI_N
CS_N
GPAI+
VSSD
CB5
ALERT_N
FAULT_N
GPIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18 19 20
21 22
23
24
25 26
27
28 29
30 31 32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
4950515253
54
55
56
57
58596061626364
P0071-04
PAP Package
(Top View)
bq78PL536
TQFP-64
bq76PL536-Q1
SLUSAB1 –MAY 2011 www.ti.com
PIN
TYPE
(1)
DESCRIPTION
NAME NO.
VC2 9 AI Sense voltage input terminal for the positive terminal of the second cell
VC3 7 AI Sense voltage input terminal for the positive terminal of the third cell
VC4 5 AI Sense voltage input terminal for the positive terminal of the fourth cell
VC5 3 AI Sense voltage input terminal for the positive terminal of the fifth cell
VC6 1 AI Sense voltage input terminal for the positive terminal of the sixth cell
VREF 16 P Internal analog voltage reference (+), requires 10-µF, low-ESR ceramic capacitor to AGND for stability
VSS 14, P V
SS
33,
34, 35
VSSD 25, 49 P V
SS
Thermal – – Thermal pad on bottom of PowerPAD™ package; this must be soldered to similar-size copper area on
pad PCB and connected to VSS, to meet stated specifications herein. Provides heat-sinking to part.
PINOUT DIAGRAM
4 Copyright © 2011, Texas Instruments Incorporated