Datasheet

PROTECTED
REGISTER
EPROM
ERRORCHECK /
CORRECT (ECC) LOGIC
7
LOAD
PROGRAM
7
PARITY
ECC_COR
ECC_ERR
REFRESH
POR
REFRESH-PROTECT KEY
VOLTAGE &
TIMINGCONTROL
PGM-PROTECT KEY
WRITE-PROTECTKEY
WRITE
LOADsignalevaluates
ECCsyndromebits
KEY requiressequenced
writetounlockfunction
6
6
5
5
4
4
3
3
2
2
1
1
0
0 P
PARITY LOGIC
CHECKBITS
INTERNAL DATA BUS
SYNDROMECHECKER / GENERATOR
C
n+1...
C
n
C
0
REGISTERCONTROL & STATUSBITS
STATUSFLAGS
Nodirectaccesstothisregister.
1 biterror
2+ biterrors
CRCCHECKLOGIC
SPIDE-SERIALIZER
bq76PL536-Q1
SLUSAB1 –MAY 2011 www.ti.com
Read / Write, Initialized From EPROM (Group3)
These registers control the device configuration and functionality. The contents of the registers are initialized
from EPROM-stored constants as a result of POR, RESET command, or the RELOAD_SHADOW command.
This feature ensures that the secondary protector portion of the device (COV, CUV, OT) is fully functional after
any reset, without host CPU involvement.
These registers may only be modified by using a special, sequential-write sequence to guard against accidental
changes. The value loaded from EPROM at reset (or by command) may be temporarily overridden by using the
special write sequence. The temporary value is overwritten to the programmed EPROM initialization value by the
next reset or command to reload. To write to a these protected registers, first write 0x35 to SHDW_CONTROL[],
immediately followed by the write to the desired register. Any intervening write cancels the special sequence.
To re-initialize the entire set of Group3 registers to the EPROM defaults, write the value 0x27 to
SHDW_CONTROL[].
These registers are further protected against corruption by a ninth parity bit that is automatically updated when
the register is written using even parity. If the contents of the register ever become corrupted, the bad parity
causes the ALERT_STATUS[PARITY] bit to become set, alerting the host CPU of the problem.
The EPROM-stored constants are programmed by writing the values to the register(s), then applying the
programming voltage to the LDODx pins, then issuing the EPROM_WRITE command to register E_EN[]. All
Group3 registers are programmed simultaneously, and this operation can only be performed once to the
one-time-programmable (OTP) memory cells. The process is not reversible.
Figure 14. Protected Register Group3 Architecture, Simplified View
Error Checking and Correcting (ECC) EPROM
The EPROM used to initialize this group is also protected by error-check-and-correct (ECC) logic. The ECC bits
provide a highly reliable storage solution in the presence of external disturbances. This feature cannot be
disabled by user action. Implementation is fully self-contained and automatic and requires no special
computations or provisioning by the user.
When the Group3 contents are permanently written to EPROM, an additional array of hidden ECC-OTP cells is
also automatically programmed. The ECC logic implements a Hamming code that automatically corrects all
single-bit errors in the EPROM array, and senses additional multi-bit errors. If any corrections are made, the
DEVICE_STATUS[ECC_COR] flag bit is set. If any multi-bit errors are sensed, the ALERT_STATUS[ECC_ERR]
flag is set. The corrective action or detection is performed anytime the contents of EPROM are loaded into the
registers – POR, RESET, or by SHADOW_LOAD command. Note: The ECC_COR and ECC_ERR bits may
glitch during OTP-EPROM writes; this is normal. If this occurs, reset the tripped bit; it should remain cleared.
34 Copyright © 2011, Texas Instruments Incorporated