Datasheet

bq76PL536-Q1

www.ti.com

SLUSAB1 –MAY 2011

GPIO

The bq76PL536-Q1 includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT] bit.

The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and then read

the IO_CONTROL[GPIO_IN] bit. A pullup (10 kΩ–1 MΩ, typ.) is required on this pin if used as an input. If the

pullup is not included in the design, system firmware must program a 0 in IO_CONTROL[GPIO_OUT] to prevent

excess current draw from the floating input. Use of a pullup is recommended in all designs to prevent an

unintentional increase in current draw.

SLEEP Functionality

The bq76PL536-Q1 provides the host a mechanism to put the part into a low-power sleep state by setting the

IO_CONTROL[SLEEP] bit. When this bit is set/reset, the following actions occur:

Sleep State Entry (bit set)

If a conversion is in progress, the device waits for it to complete, then sets DRDY true (high).

The device sets the ALERT_STATUS[SLEEP] bit, which in turn causes the ALERT pin to be asserted.

The device gates off all other sources of FAULT or ALERT except ALERT[SLEEP]. The existing state of the

FAULT and ALERT registers is preserved. The host should service and reset the ALERT generated by the

SLEEP bit being set to minimize SLEEP state current draw by writing a 1 to ALERT[SLEEP] followed by a 0 to

ALERT[SLEEP]. The ALERT North-South signal chain can draw up to ~1 mA of current when active, so this

ALERT source should be cleared prior to the host entering the SLEEP state of its own. This signaling is provided

to notify the host that the unmonitored/unprotected state is being entered.

The REG50 LDO is shut down and the output is allowed to float. The ADC, its reference, and clocks are

disabled. The COV, CUV, and OT circuits are disabled, and their band-gap reference shut off. Note that this

effectively removes protection and monitoring from the cells; the designer should take the necessary

design steps and verifications to ensure the cells cannot be put into an unsafe condition by other parts

of the system or usage characteristics.

IO_CONTROL[TS1(2)] bits are not modified. The host must also set these bits to zero to minimize current draw

of the thermistors themselves.

SPI communications are preserved; all registers may be read or written.

Sleep State Exit (Bit Reset)

VREG50 operation is restored.

COV, CUV, OT circuits are re-enabled.

The ADC circuitry returns to its former state. Note that there is a warm-up delay associated with the ADC enable,

the same delay as specified for enabling from a cold start.

The FAULT and ALERT registers are restored to their pre-SLEEP state. If a FAULT or ALERT condition was

present prior to SLEEP, the FAULT or ALERT pin is immediately asserted.

IO_CONTROL[TS1(2)] should be set by the host if the OT function or temperature measurement functions are

desired.

COMMUNICATIONS

SPI Communications – Device to Host

Device-to-host (D2H) mode is provided on the SPI interface pins for connection to a local host microcontroller,

logic, etc. D2H communications operate in voltage mode as a standard SPI interface for ease of connection to

the outside world from the bq76PL536-Q1 device. Standard TTL-compatible logic levels are presented. All

relevant SPI timing and performance parameters are met by this interface.

The host interface operates in SPI mode 1, where CPOL = 0 and CPHA = 1. The SPI clock is normally low; data

changes on rising edges, and is sampled on the falling edge. All transfers are MSB-first.