Datasheet

bq76PL536A-Q1
www.ti.com SLUSAM3 –MAY 2011
ADDRESS_CONTROL REGISTER (0x3b)
7 6 5 4 3 2 1 0
AR 0 ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
The ADDRESS_CONTROL register allows the host to assign an address to the bq76PL536A-Q1 for
communication. The default for this register is 0x00 at RESET.
[7] (ADDR_RQST): This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct
address. This bit is reflected in the DEVICE_STATUS[AR] bit
0 = Address has not been assigned (default at RESET).
1 = Address has been assigned.
[5..0] (ADDR): These bits set the device address for SPI communication. This provides to a range of
addresses from 0x00 to 0x3f. Address 0x3f is reserved for broadcast messages to all
connected and addressed 76PL536 devices. The default for these 6 bits is 0x00 at
RESET.
RESET REGISTER (0x3c)
7 6 5 4 3 2 1 0
RST[7] RST[6] RST[5] RST[4] RST[3] RST[2] RST[1] RST[0]
The RESET register allows the host to reset the bq76PL536A-Q1 directly.
Writing 0xa5 causes the device to RESET. Other values are ignored.
TEST_SELECT REGISTER (0x3d)
7 6 5 4 3 2 1 0
TSEL[7] TSEL[6] TSEL[5] TSEL[4] TSEL[3] TSEL[2] TSEL[1] TSEL[0]
The TEST_SELECT places the SPI port in a special mode useful for debug.
TSEL (b7–b0) is used to place the SPI_H interface pins in a mode to support test/debug of a string of
bq76PL536A-Q1 devices. 0 = normal operating mode.
When the sequence 0xa4, 0x25 ("JR") is written on subsequent write cycles, the device enters a special TEST
mode useful for stack debugging. Writes to other registers between the required sequence bytes results in the
partial sequence being voided; the entire sequence must be written again. POR, RESET, or writing a 0x00 to this
register location exits this mode.
In this state, SPI pin SCLK and SDI become outputs and are enabled, and reflect the state of the SCLK_S,
SDI_S pins of the device. SDO remains an output. This allows observation of bus traffic mid-string. The lowest
device in the string should not be set to operate in this mode. The user is cautioned to condition the connection
to a mid- or top-string device with suitable isolation circuitry to prevent injury or damage to connected devices.
Programming the most-negative device on the stack in this mode prevents further communications with the stack
until POR, and may result in device destruction; this condition should be avoided.
E_EN REGISTER (0x3f)
7 6 5 4 3 2 1 0
E_EN[7] E_EN [6] E_EN [5] E_EN [4] E_EN [3] E_EN [2] E_EN [1] E_EN [0]
The E_EN register controls the access to the programming of the integrated OTP EPROM.
This register should be written the value 0x91 to permit writing the USER block of EPROM. Values other than
0x00 and 0x91 are reserved and may result in undefined operation. The next read or write of any type to the
device resets (closes) the write window. If a Group3 protected write occurs, the window is closed after the write.
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