Datasheet

www.ti.com
Communicating with the bq27210 (I
2
C interface - Product Preview)
Hostgenerated bq27210generated
A AS 0ADDR[6:0] CMD[7:0]
Sr
1ADDR[6:0] A DATA[7:0] A DATA[7:0] PN...
(d)
A AS 0ADDR[6:0] CMD[7:0]
Sr
1ADDR[6:0] A DATA[7:0] PN
(c)
A AS A0 PADDR[6:0] CMD[7:0] DATA[7:0]
(a)
(b)
S 1ADDR[6:0] A DATA[7:0] PN
A AS N0 PADDR[6:0] CMD[7:0] DATA[7:0]
AS N0 PADDR[6:0] CMD[7:0]
. . .A AS A0 PADDR[6:0] CMD[7:0] DATA[7:0] DATA[7:0] N N
A AS 0ADDR[6:0] CMD[7:0] Sr 1ADDR[6:0] A DATA[7:0] A DATA[7:0] PN
Address
0x7F
Data from
addr 0x7F
Data from
addr 0x00
bq27010 , bq27210
SLUS707B – APRIL 2006 – REVISED JANUARY 2007
The bq27210 supports the standard I
2
C read, incremental read, quick read, and one byte write functions. The
7-bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as 1010101. The 8-bit
device address is therefore 0xAA or 0xAB for write or read, respectively. (S = Start, Sr = Repeated Start, A =
Acknowledge, N = No Acknowledge, and P = Stop)
Figure 7. Supported I2C formats :
(a) 1-byte write; (b) quick read; (c) 1-byte read; (d) incremental read
The incremental read protocol is recommended for reading all 16-bit values, as this ensures that the 16-bit value
is not updated during the time interval between reading the two bytes of data (see previous section on reading
16-bit values). The quick read returns data at the address indicated by the internal address pointer. The address
pointer is incremented after each data byte is read or written. Reading an even address causes the
communication engine to simultaneously capture the data byte from the requested even address and the data
byte from the next odd address, and the address pointer is incremented twice. The data byte captured from the
next odd address is output if the communication continues, without a stop, after the host acknowledges the even
address byte.
Due to the memory map setup of the device, several boundary conditions must be enforced by the
communication engine.
Attempt to write a read-only address (NACK after data sent by master):
Attempt to read an address above 0x7F (NACK command):
Attempt at incremental writes (NACK all extra data bytes sent):
Incremental read at the maximum allowed read address:
The I
2
C engine releases both SDA and SCL if the I
2
C bus is held low for T
(BUSERR)
. If the bq27210 is holding the
lines, releasing them frees the master to drive the lines. If an external condition is holding either of the lines low,
the I
2
C engine enters the low-power sleep mode if the measured charge/discharge activity level is less than the
DMF threshold.
27
Submit Documentation Feedback