Datasheet

/ PGOOD= Low
V
UVLO
<V
IN
<V
OVP
and
V
IN
>V
BAT
+V
IN (DT)
No
Yes
EN1=EN2=1
Yes
No
ILIMorISET short?
Yes
/ PGOOD= Hi-Z
/CHG = Hi-Z
BATTFET ON
BeginStartup
IIN (MAX ) 100mA
V
OUT
short?
Yes
No
No
InputCurrent
LimitsetbyEN1
andEN2
/CE = Low
No
BeginCharging
Yes
bq24072T
bq24075T, bq24079T
SLUS937A DECEMBER 2009REVISED APRIL 2010
www.ti.com
POWER ON
When VIN exceeds the UVLO threshold, the bq2407xT powers up. While V
IN
is below V
BAT
+ V
IN(DT)
, the host
commands at the control inputs (CE, EN1 and EN2) are ignored. The Q1 FET connected between IN and OUT
pins is off, and the status outputs CHG and PGOOD are high impedance. The Q2 FET that connects BAT to
OUT is ON. (If SYSOFF is high, Q2 is off). During this mode, the V
OUT(SC2)
circuitry is active and monitors for
overload conditions on OUT.
Once V
IN
rises above V
BAT
+ V
IN(DT)
, PGOOD is driven low to indicate the valid power status and the CE, EN1,
and EN2 inputs are read. The device enters standby mode if (EN1 = EN2 = HI) or if an input overvoltage
condition occurs. In standby mode, Q1 is OFF and Q2 is ON so OUT is connected to the battery input. (If
SYSOFF is high, FET Q2 is off). During this mode, the V
OUT(SC2)
circuitry is active and monitors for overload
conditions on OUT.
When the input voltage at IN is within the valid range: V
IN
> UVLO AND V
IN
> V
BAT
+ V
IN(DT)
AND V
IN
< V
OVP
, and
the EN1 and EN2 pins indicate that the USB suspend mode is not enabled [(EN1, EN2) (HI, HI)] all internal
timers and other circuit blocks are activated. The device then checks for short-circuits at the ISET and ILIM pins.
If no short conditions exists, the device switches on the input FET Q1 with a 100mA current limit to checks for a
short circuit at OUT. When V
OUT
is above V
SC
, the FET Q1 switches to the current limit threshold set by EN1,
EN2 and R
ILIM
and the device enters into the normal operation. During normal operation, the system is powered
by the input source (Q1 is regulating), and the device continuously monitors the status of CE, EN1 and EN2 as
well as the input voltage conditions.
Figure 27. Startup Flow Diagram
16 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): bq24072T bq24075T bq24079T