Datasheet

Last Measured Discharge Register (LMD)
LMD is the register (address=05h) that the bq2050H
uses as a measured full reference. The bq2050H adjusts
LMD based on the measured discharge capacity of the
battery from full to empty. In this way the bq2050H up
-
dates the capacity of the battery. LMD is set to PFC
during a bq2050H reset.
LMD is set to DCR upon the first valid charge after EDV
is set if VDQ is set.
If DCR < 0.94 LMD, then LMD is set to 0.94 ∗ LMD.
Secondary Status Flags Register (FLGS2)
The FLGS2 register (address=06h) contains the secon
-
dary bq2050H flags.
Bit 7 and bit 1 of FLGS2 are reserved. Do not write to
these bits.
The discharge rate flags, DR2–0, are bits 6–4.
They are used to determine the current discharge re-
gime as follows:
The enable interrupt flag (ENINT) is a test bit used to
determine V
SR
activity sensed by the bq2050H. The
state of this bit will vary and should be ignored by the
system.
The valid charge flag (VQ), bit 2 of FLGS2, is used to
indicate whether the bq2050H recognizes a valid charge
condition. This bit is reset on the first discharge after
NAC = LMD.
The VQ values are:
Where VQ is:
0 Valid charge action not detected between a
discharge from NAC = LMD and EDV1
1 Valid charge action detected
The overload flag (OVLD) is asserted when a discharge
rate in excess of 2C is detected. OVLD remains asserted
as long as the condition persists and is cleared 0.5 sec
-
onds after the rate drops below 2C. The overload condi
-
tion is used to stop sampling of the battery terminal char
-
acteristics for end-of-discharge determination.
Program Pin Pull-Down Register (PPD)
The PPD register (address=07h) contains some of the pro
-
gramming pin information for the bq2050H. The segment
drivers, SEG
1–5
, have a corresponding PPD register loca
-
tion, PPD
1–5
. A given location is set if a pull-down resis-
tor has been detected on its corresponding segment driver.
For example, if SEG
1
and SEG
4
have pull-down resistors,
the contents of PPD are xxx01001.
Program Pin Pull-Up Register (PPU)
The PPU register (address=08h) contains the rest of the
programming pin information for the bq2050H. The seg-
ment drivers, SEG
1–5
, have a corresponding PPU register
location, PPU
1–5
. A given location is set if a pull-up resis-
tor has been detected on its corresponding segment driver.
For example, if SEG
3
and SEG
5
have pull-up resistors, the
contents of PPU are xxx10100.
Capacity Inaccurate Count Register (CPI)
The CPI register (address=09h) is used to indicate the
number of times a battery has been charged without an
LMD update. Because the capacity of a rechargeable
battery varies with age and operating conditions, the
bq2050H adapts to the changing capacity over time. A
complete discharge from full (NAC=LMD) to empty
(EDV1=1) is required to perform an LMD update assum
-
ing there have been no intervening valid charges, the
temperature is greater than or equal to 0°C, and there
has been no more than a 6% self-discharge reduction.
15
bq2050H
PPD/PPU Bits
7 6 5 43210
RSVD RSVD RSVD PPU
5
PPU
4
PPU
3
PPU
2
PPU
1
RSVD RSVD RSVD PPD
5
PPD
4
PPD
3
PPD
2
PPD
1
FLGS2 Bits
76543 2 1 0
- - - - - - - OVLD
FLGS2 Bits
7 6 5 4 3210
- DR2 DR1 DR0 - - -
DR2 DR1 DR0 Discharge Rate
0 0 0 DRATE
<
0.5C
0 0 1 0.5C
≤
DRATE
<
2C
0 1 0 2C < DRATE
FLGS2 Bits
76543210
- - - - ENINT - -
FLGS2 Bits
76543210
-----VQ-