Datasheet

AFE031
SBOS531D –AUGUST 2010–REVISED MAY 2012 www.ti.com
PIN DESCRIPTIONS
DAC (Pin 7)
The DAC pin is used to configure the SPI to either read or write data to the Command and Data Registers, or to
write data to the DAC register. Setting the DAC pin high allows access to the DAC register. Setting the DAC pin
low allows access to the Command and Data Registers.
SD (Pin 8)
The Shutdown pin (SD) can be used to shut down the entire AFE031 for maximum power savings. When the SD
pin is low, normal operation of the AFE031 occurs. When the SD pin is high, all circuit blocks within the AFE031,
including the serial interface, are placed into the lowest-power operating modes. In this condition, the entire
AFE031 draws only 95 μA of current. All register contents at the time the AFE031 is placed into shutdown mode
are saved; upon re-enabling the AFE031, the register contents retain the respective saved values.
INT Pin (9)
The Interrupt pin (INT) can be used to signal the microprocessor of an unusual operating condition that results
from an anomaly on the ac mains. The INTpin can be triggered by two external circuit conditions, depending
upon the Enable Register settings. The AFE031 can be programmed to issue an interrupt on these conditions:
• Current Overload
• Thermal Overload
Current Overload
The maximum output current allowed from the Power Amplifier can be programmed with the external R
SET
resistor connected between PA_ISET (pin 46) and ground. If a fault condition should occur and cause an
overcurrent event for the PA, the PA goes into current limit and the I_FLAG bit (location 6 in the RESET
Register) is set to a '1' if the I_Flag_EN bit (location 6 in the Control2 Register) is enabled. This configuration
results in an interrupt signal at the INT pin. The I_FLAG bit remains set to '1' even after the device returns to
normal operation. The I_FLAG bit remains at '1' until it is reset by the microprocessor.
If the I_FLAG_EN bit (location 6 in the Control2 Register) is disabled and a current overload condition occurs, the
PA goes into current-limit mode to protect the AFE031; however, the contents of the I_FLAG bit (location 6 in the
RESET Register) remain at the respective previous values (presumably '0' for normal operation), and the
AFE031 does not issue an interrupt at the INT pin.
Thermal Overload
The AFE031 contains internal protection circuitry that automatically disables the PA output stage if the junction
temperature exceeds +150°C. If a fault condition occurs that causes a thermal overload, and if the T_FLAG_EN
bit (location 5 in the Control2 Register) is enabled, the T_FLAG bit (location 5 in the RESET Register) is set to a
'1'. This configuration results in an interrupt signal at the INT pin. The AFE031 includes a thermal hysteresis and
allows the PA to resume normal operation when the junction temperature reduces to +135°C. The T_FLAG bit
remains set to a '1' even after the device returns to normal operation. The T_FLAG bit remains '1' until it is reset
by the microprocessor.
If the T_FLAG_EN bit (location 5 in the Control2 Register) is disabled and a thermal overload condition occurs,
the PA continues to go into thermal limit and protect the AFE031, but the contents of the T_FLAG bit (location 5
in the RESET Register) remain at the previous value (presumably '0' for normal operation), and the AFE031 does
not issue an interrupt at the INT pin.
Once an interrupt is signaled (that is, INT goes low), the contents of the I_FLAG and T_FLAG bits can be read
by the microprocessor to determine the type of interrupt that occurred. Using the Control2 Register, each
interrupt type (current or thermal) can be individually enabled or disabled, allowing full user customization of the
INT function. For proper operation of the interrupt pin it is recommended to configure the interrupt enable
registers in the Control2 Register by writing to bit locations 5, 6, and 7 following the information in Table 18 after
each time the AFE031 is powered on. Failure to properly configure bit locations 5, 6, and 7 after power on may
result in unexpected interrupt signals.
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