Datasheet

ADS8556
ADS8557
ADS8558
www.ti.com SBAS404B –OCTOBER 2006– REVISED JANUARY 2012
ELECTRICAL CHARACTERISTICS: GENERAL
Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V,
HVDD = 10V to 15V, HVSS = –15V to –10V, V
REF
= 2.5V (internal), and f
DATA
= maximum, unless otherwise noted.
ADS8556, ADS8557, ADS8558
PARAMETER CONDITIONS MIN TYP
(1)
MAX UNIT
ANALOG INPUT
RANGE pin/RANGE bit = 0 –4 × V
REF
+4 × V
REF
V
Bipolar full-scale range CHXX
RANGE pin/RANGE bit = 1 –2 × V
REF
+2 × V
REF
V
Input range = ±4 × V
REF
10 pF
Input capacitance
Input range = ±2 × V
REF
20 pF
Input leakage current No ongoing conversion ±1 μA
Aperture delay 5 ns
Aperture delay matching Common CONVST for all channels 250 ps
Aperture jitter 50 ps
EXTERNAL CLOCK INPUT (XCLK)
External clock frequency f
XCLK
An external reference must be used for f
XCLK
> f
CCLK
1 18 20 MHz
External clock duty cycle 45 55 %
REFERENCE VOLTAGE OUTPUT (REF
OUT
)
2.5V operation, REFDAC = 0x3FF 2.485 2.5 2.515 V
2.5V operation, REFDAC = 0x3FF at +25°C 2.496 2.5 2.504 V
Reference voltage V
REF
3.0V operation, REFDAC = 0x3FF 2.985 3.0 3.015 V
3.0V operation, REFDAC = 0x3FF at +25°C 2.995 3.0 3.005 V
Reference voltage drift dV
REF
/dT ±10 ppm/°C
Power-supply rejection ratio PSRR 73 dB
Output current I
REFOUT
DC current –2 2 mA
Short-circuit current
(2)
I
REFSC
50 mA
Turn-on settling time t
REFON
10 ms
At CREF_x pins 4.7 10 μF
External load capacitance
At REFIO pins 100 470 nF
Tuning range REFDAC Internal reference output voltage range 0.2 × V
REF
V
REF
V
REFDAC resolution 10 Bits
REFDAC differential nonlinearity DNL
DAC
–1 ±0.1 1 LSB
REFDAC integral nonlinearity INL
DAC
–2 ±0.1 2 LSB
REFDAC offset error V
OSDAC
V
REF
= 0.5V (DAC = 0x0CC) –4 ±0.65 4 LSB
REFERENCE VOLTAGE INPUT (REF
IN
)
Reference input voltage V
REFIN
0.5 2.5 3.025 V
Input resistance 100 MΩ
Input capacitance 5 pF
Reference input current 1 μA
SERIAL CLOCK INPUT (SCLK)
Serial clock input frequency f
SCLK
0.1 36 MHz
Serial clock period t
SCLK
0.0278 10 μs
Serial clock duty cycle 40 60 %
DIGITAL INPUTS
(3)
Logic family CMOS with Schmitt-Trigger
High-level input voltage 0.7 × BVDD BVDD + 0.3 V
Low-level input voltage BGND – 0.3 0.3 × BVDD V
Input current V
I
= BVDD to BGND –50 +50 nA
Input capacitance 5 pF
(1) All values are at T
A
= +25°C.
(2) Reference output current is not limited internally.
(3) Specified by design.
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