Datasheet

START OF A CONVERSION AND READING
1 2 16 17 18 19 20 1 2
CONVERSION ACQUISITION
CLK
HOLDB
EOC
CS
RD
A0
ADS8365
SBAS362C – AUGUST 2006 – REVISED MARCH 2008 .................................................................................................................................................... www.ti.com
The ADS8365 can also convert one channel
DATA continuously (see Figure 28 ). Therefore, HOLDA and
HOLDC are kept high all the time. To gain acquisition
By bringing one, two, or all three of the HOLDX
time, the falling edge of HOLDB takes place just
signals low, the input data of the corresponding
before the rising edge of clock. One conversion
channel X are immediately placed in the hold mode
requires 20 clock cycles. Here, data are read after the
(5ns). The conversion of this channel X follows with
next conversion is initiated by HOLDB. To read data
the next rising edge of clock. If it is important to
from channel B, A1 is set high and A2 is low. Since
detect a hold command during a certain clock-cycle,
A0 is low during the first reading (A2 A1 A0 = 010),
then the falling edge of the hold signal has to occur at
data B0 are put to the output. Before the second RD,
least 10ns before the rising edge of clock, as shown
A0 switches high (A2 A1 A0 = 011) so that data from
in Figure 27 , t
D1
. The hold signal can remain low
channel B1 are read, as shown in Table 1 . However,
without initiating a new conversion. The hold signal
reading data during the conversion or on a falling
must be high for at least 15ns (as shown in
hold edge might cause a loss in performance.
Figure 27 , t
W2
) before it is brought low again, and
hold must stay low for at least 20ns (Figure 27 , t
W3
).
Table 1. Address Control for RD Functions
Once a particular hold signal goes low, further
A2 A1 A0 CHANNEL TO BE READ
impulses of this hold signal are ignored until the
0 0 0 CH A0
conversion is finished or the device is reset. When
0 0 1 CH A1
the conversion is finished (after 16 clock cycles) the
0 1 0 CH B0
sampling switches close and sample the selected
channel. The start of the next conversion must be
0 1 1 CH B1
delayed to allow the input capacitor of the ADS8365
1 0 0 CH C0
to be fully charged. This delay time depends on the
1 0 1 CH C1
driving amplifier, but should be at least 800ns.
Cycle mode reads registers CH A0
1 1 0 to CH C1 on successive transitions
of the read line
1 1 1 FIFO mode
Figure 28. Timing of One Conversion Cycle
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