Datasheet

ADS8363
ADS7263
ADS7223
SBAS523B –OCTOBER 2010–REVISED JANUARY 2011 www.ti.com
Sequencer/FIFO (SEQFIFO) Register
The ADS8363/7363/7223 feature a programmable sequencer that controls the switching of the ADC input
multiplexer in pseudo-differential, automatic channel-selection mode only. When used, a single read pulse allows
reading of all stored conversion data. A single CONVST is required to control the conversion of the entire
sequence. If the sequencer is used, CONVST and RD must be controlled independently (see Figure 32 and
Figure 33).
Additionally, a programmable FIFO is available on each channel that allows for storing up to four conversion
results. Both features are controlled using this register. If FIFO is used, CONVST and RD must be controlled
independently. Note that after activation of this feature, the FIFO should be full before being read for the first
time.
If the FIFO is full and a new conversion starts, the contents are shifted by one while the oldest result is lost. Only
when the sequencer is used are the entire FIFO contents lost (that is, all bits are automatically set to '0'). The
FIFO can be used independently from the sequencer. When both are used, the complete sequence must be
finished before reading the data out of the FIFO; otherwise, the data may be corrupted.
Table 10 contains details of the data readout requirements depending on the FIFO settings in automatic channel
selection mode.
Table 10. Conversion Result Read Out in FIFO Mode
AUTOMATIC CHANNEL SELECTION
INPUT SIGNAL TYPE FE = '0' FE = '1'
Fully-differential input Read cycle length = 1 word Read cycle length = 2 · FIFO length
mode One RD pulse required after each conversion One RD pulse required for the entire FIFO content
Read cycle length = 1 word Read cycle length = 2 · sequencer length · FIFO
Pseudo-differential input
One RD pulse required after each conversion or after length
mode
completing the sequence if S1 = '1' and S0 = '1' One RD pulse required for the entire FIFO content
Table 11. SEQFIFO: Sequencer and FIFO Register (default = 0000h)
(1)
MSB LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
S1 S0 SL1 SL0 C11 C10 C21 C20 C31 C30 C41 C40 SP1 SP0 FD1 FD0
(1) The sequencer is used in pseudo-differential mode only; this register should be set before setting the REFCM register.
Bits[15:14] S[1:0]—Sequencer mode selection (see Figure 32) in pseudo-differential mode only.
These bits allow for the control of the number of CONVSTs required, and the behavior of the BUSY pin in Sequencer
mode.
0x = An individual CONVST is required with BUSY indicating each conversion (default).
10 = A single CONVST is required for the entire sequence with BUSY indicating each conversion (half-clock mode only).
11 = A single CONVST is required for the entire sequence with BUSY remaining high throughout the sequence
(half-clock mode only)
Bits[13:12] SL[1:0] Sequencer length control.
These bits control the length of a sequence. Bits [11:6] are only active if SL > '00'.
00 = Do not use; use Mode I or II instead, where M0 = '0' (default).
01 = Sequencer length = 2; C1x (bits[11:10]) and C2x (bits[9:8]) define the actual channel selection.
10 = Sequencer length = 3; C1x (bits[11:10]), C2x (bits[9:8]) and C3x (bits[7:6]) define the actual channel selection.
11 = Sequencer length = 4; C1x (bits[11:10]), C2x (bits[9:8]), C3x (bits[7:6]), and C4x (bits[5:4]) define the actual channel
selection.
Bits[11:10] C1[1:0]—First channel in sequence selection bits.
Bits[9:8] C2[1:0]—Second channel in sequence selection bits.
Bits[7:6] C3[1:0]—Third channel in sequence selection bits.
Bits[5:4] C4[1:0]—Fourth channel in sequence selection bits.
Bits [11:4] control the pseudo-differential input multiplexer channel selection in sequencer mode.
00 = CHA0 and CHB0 are selected for the next conversion (default).
01 = CHA1 and CHB1 are selected for the next conversion.
10 = CHA2 and CHB2 are selected for the next conversion.
11 = CHA3 and CHB3 are selected for the next conversion.
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