Datasheet

ADS8343
12
SBAS183C
www.ti.com
A2 A1 A0 CH0 CH1 CH2 CH3 COM
001+IN–IN
101–IN +IN
010 +IN–IN
110 –IN +IN
TABLE IV. Differential Channel Control (SGL/DIF LOW).
Bit 7 Bit 0
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB)
S A2A1A0—
SGL/DIF
PD1 PD0
TABLE I. Order of the Control Bits in the Control Byte.
TABLE II. Descriptions of the Control Bits within the Control Byte.
BIT NAME DESCRIPTION
7 S Start Bit. Control byte starts with first HIGH bit on
DIN.
6-4 A2-A0 Channel Select Bits. Along with the
SGL/DIF
bit,
these bits control the setting of the multiplexer input.
2
SGL/DIF
Single-Ended/Differential Select Bit. Along with bits
A2-A0, this bit controls the setting of the multiplexer
input.
1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for
details.
A2 A1 A0 CH0 CH1 CH2 CH3 COM
001+IN –IN
101 +IN –IN
010 +IN –IN
110 +IN–IN
TABLE III. Single-Ended Channel Selection (SGL/DIF HIGH).
size, as the reference voltage is reduced. For example, if the
offset of a given converter is 2LSBs with a 2.5V reference,
then it will typically be 10LSBs with a 0.5V reference. In each
case, the actual offset of the device is the same, 76µV.
The noise or uncertainty of the digitized output will increase
with lower LSB size. With a reference voltage of 500mV, the
LSB size is 7.6µV. This level is below the internal noise of the
device. As a result, the digital output code will not be stable
and vary around a mean value by a number of LSBs. The
distribution of output codes will be gaussian and the noise
can be reduced by simply averaging consecutive conversion
results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low-noise, low-ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the V
REF
input is not buffered and directly
drives the Capacitor Digital-to-Analog Converter (CDAC)
portion of the ADS8343. Typically, the input current is 13µA
with a 2.5V reference. This value will vary by microamps
depending on the result of the conversion. The reference
current diminishes directly with both conversion rate and
reference voltage. As the current from the reference is drawn
on each bit decision, clocking the converter more quickly
during a given conversion period will not reduce overall
current drain from the reference.
DIGITAL INTERFACE
Figure 6 shows the typical operation of the ADS8343’s digital
interface. This diagram assumes that the source of the digital
signals is a microcontroller or digital signal processor with a
basic serial interface (note that the digital inputs are over-
voltage tolerant up to 5.5V, regardless of +V
CC
). Each com-
munication between the processor and the converter con-
sists of eight clock cycles. One complete conversion can be
accomplished with three serial communications, for a total of
24 clock cycles on the DCLK input.
The first eight cycles are used to provide the control byte via
the DIN pin. When the converter has enough information
about the following conversion to set the input multiplexer
appropriately, it enters the acquisition (sample) mode. After
three more clock cycles, the control byte is complete and the
converter enters the conversion mode. At this point, the input
sample-and-hold goes into the hold mode. The next 16 clock
cycles accomplish the actual A/D conversion.
Control Byte
Also shown in Figure 6 is the placement and order of the
control bits within the control byte. Tables I and II give
detailed information about these bits. The first bit, the ‘S’ bit,
must always be HIGH and indicates the start of the control
byte. The ADS8343 will ignore inputs on the DIN pin until the
start bit is detected. The next three bits (A2-A0) select the
active input channel or channels of the input multiplexer, as
shown in Tables III and IV and Figure 5.
FIGURE 6. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.
t
ACQ
AcquireIdle Conversion
1DCLK
CS
81
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2S
DIN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0 Zero Filled...
81 8
AcquireIdle Conversion
181
15
(MSB)
(START)
A2SA1A0
SGL/
DIF
PD1 PD0
14