Datasheet

ADS8326
www.ti.com .................................................................................................................................................. SBAS343C –MAY 2007–REVISED SEPTEMBER 2009
DIGITAL INTERFACE A falling CS signal initiates the conversion and data
transfer. The first 4.5 to 5.0 clock periods of the
Signal Levels conversion cycle are used to sample the input signal.
After the fifth falling DCLOCK edge, D
OUT
is enabled
The ADS8326 has a wide range of power-supply
and will output a low value for one clock period. For
voltage. The A/D converter, as well as the digital
the next 16 DCLOCK periods, D
OUT
will output the
interface circuit, is designed to accept and operate
conversion result, most significant bit first. After the
from 2.7V up to 5.5V. This voltage range will
least significant bit (B0) has been output, subsequent
accommodate different logic levels. When the
clocks will repeat the output data, but in a least
ADS8326 power-supply voltage is in the range of
significant bit first format.
4.5V to 5.5V (5V logic level), the ADS8326 can be
connected directly to another 5V, CMOS-integrated After the most significant bit (B15) has been
circuit. When the ADS8326 power-supply voltage is in repeated, D
OUT
will tri-state. Subsequent clocks will
the range of 2.7V to 3.6V (3V logic level), the have no effect on the converter. A new conversion is
ADS8326 can be connected directly to another 3.3V initiated only when CS has been taken high and
LVCMOS integrated circuit. returned low.
Serial Interface Data Format
The ADS8326 communicates with microprocessors The output data from the ADS8326 is in Straight
and other digital systems via a synchronous 3-wire Binary format, as shown in Figure 43. This figure
serial interface, as illustrated in the Timing represents the ideal output code for a given input
Information section. The DCLOCK signal voltage and does not include the effects of offset,
synchronizes the data transfer, with each bit being gain error, or noise.
transmitted on the falling edge of DCLOCK. Most
receiving systems will capture the bitstream on the
rising edge of DCLOCK. However, if the minimum
hold time for D
OUT
is acceptable, the system can use
the falling edge of DCLOCK to capture each bit.
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