Datasheet

ADS8323
SBAS224C –DECEMBER 2001–REVISED JANUARY 2010 www.ti.com
LAYOUT On average, the ADS8323 draws very little current
from an external reference, as the reference voltage
For optimum performance, care should be taken with
is internally buffered. If the reference voltage is
the physical layout of the ADS8323 circuitry. This
external and originates from an op amp, make sure
consideration is particularly true if the CLOCK input is
that it can drive the bypass capacitor or capacitors
approaching the maximum throughput rate.
without oscillation. A 0.1μF bypass capacitor is
recommended from pin 31 directly to ground.
As the ADS8323 offers single-supply operation, it is
often used in close proximity with digital logic,
The AGND and DGND pins should be connected to a
microcontrollers, microprocessors, and digital signal
clean ground point. In all cases, this point should be
processors. The more digital logic present in the
the analog ground. Avoid connections which are too
design and the higher the switching speed, the more
close to the grounding point of a microcontroller or
difficult it is to achieve good performance from the
digital signal processor. If required, run a ground
converter.
trace directly from the converter to the power supply
entry point. The ideal layout includes an analog
The basic SAR architecture is sensitive to glitches or
ground plane dedicated to the converter and
sudden changes on the power supply, reference,
associated analog circuitry.
ground connections and digital inputs that occur just
before latching the output of the analog comparator.
As with the GND connections, V
DD
should be
Thus, during any single conversion for an n-bit SAR
connected to a +5V power supply plane, or trace, that
converter, there are n windows in which large
is separate from the connection for digital logic until
external transient voltages can affect the conversion
they are connected at the power entry point. Power to
result. Such glitches might originate from switching
the ADS8323 should be clean and well-bypassed. A
power supplies, or nearby digital logic or high-power
0.1μF ceramic bypass capacitor should be placed as
devices.
close to the device as possible. In addition, a 1μF to
10μF capacitor is recommended. If needed, an even
The degree of error in the digital output depends on
larger capacitor and a 5Ω or 10Ω series resistor may
the reference voltage, layout, and the exact timing of
be used to low-pass filter a noisy supply. In some
the external event. These errors can change if the
situations, additional bypassing may be required,
external event changes in time with respect to the
such as a 100μF electrolytic capacitor, or even a Pi
CLOCK input.
filter made up of inductors and capacitors all
designed to essentially low-pass filter the +5V supply,
removing the high-frequency noise.
16 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS8323