Datasheet

ADS8322
SBAS215A –JULY 2001–REVISED JANUARY 2010 www.ti.com
The AGND and DGND pins should be connected to a As with the GND connections, V
DD
should be
clean ground point. In all cases, this point should be connected to a +5V power supply plane, or trace, that
the analog ground. Avoid connections which are too is separate from the connection for digital logic until
close to the grounding point of a microcontroller or they are connected at the power entry point. Power to
digital signal processor. If required, run a ground the ADS8322 should be clean and well-bypassed. A
trace directly from the converter to the power supply 0.1μF ceramic bypass capacitor should be placed as
entry point. The ideal layout will include an analog close to the device as possible. In addition, a 1μF to
ground plane dedicated to the converter and 10μF capacitor is recommended. If needed, an even
associated analog circuitry. larger capacitor and a 5Ω or 10Ω series resistor may
be used to low-pass filter a noisy supply. In some
situations, additional bypassing may be required,
such as a 100μF electrolytic capacitor, or even a Pi
filter made up of inductors and capacitors—all
designed to essentially low-pass filter the +5V supply,
removing the high-frequency noise.
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July, 2001) to Revision A Page
• Updated document format to current standards ................................................................................................................... 1
• Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2
• Changed acquisition time specification from .4μs (max) to 350ns (min) .............................................................................. 3
• Changed acquisition time specification from .4μs (max) to 350ns (min) .............................................................................. 6
• Added Figure 12, Linearity Error and Differential Linearity Error vs Code ........................................................................... 8
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