Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 28

10-Bit, 20MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● NO MISSING CODES

● INTERNAL REFERENCE

● LOW DIFFERENTIAL LINEARITY ERROR:

0.2LSB

● LOW POWER: 195mW

● HIGH SNR: 60dB

● WIDEBAND TRACK/HOLD: 65MHz

DESCRIPTION

The ADS820 is a low-power, monolithic 10-bit, 20MHz Ana-

log-to-Digital (A/D) converter utilizing a small geometry CMOS

process. This complete converter includes a 10-bit quantizer

with internal track-and-hold, reference, and a power down

feature. It operates from a single +5V power supply and can

be configured to accept either differential or single-ended

input signals.

The ADS820 employs digital error correction to provide excel-

lent Nyquist differential linearity performance for demanding

imaging applications. Its low distortion, high SNR, and high

oversampling capability give it the extra margin needed for

telecommunications and video applications.

This high performance converter is specified for AC and

DC-performance at a 20MHz sampling rate. The ADS820

is available in an SO-28 package.

APPLICATIONS

● SET-TOP BOXES

● CABLE MODEMS

● VIDEO DIGITIZING

● CCD IMAGING

Camcorders

Copiers

Scanners

Security Cameras

● IF AND BASEBAND DIGITIZATION

ADS820

SBAS037B – DECEMBER 1995 – REVISED FEBRUARY 2005

www.ti.com

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Pipeline

A/D

Timing

Circuitry

Error

Correction

Logic

3-State

Outputs

T&H

10-Bit

Digital

Data

CLK

+1.25V

+3.25V

MSBI OE

REFT

REFB

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

All trademarks are the property of their respective owners.

Summary of content (20 pages)

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ADS820 ADS 820 U SBAS037B – DECEMBER 1995 – REVISED FEBRUARY 2005 10-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● NO MISSING CODES ● INTERNAL REFERENCE ● LOW DIFFERENTIAL LINEARITY ERROR: 0.2LSB ● LOW POWER: 195mW ● HIGH SNR: 60dB ● WIDEBAND TRACK/HOLD: 65MHz The ADS820 is a low-power, monolithic 10-bit, 20MHz Analog-to-Digital (A/D) converter utilizing a small geometry CMOS process.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +VS ....................................................................................................... +6V Analog Input ............................................................ 0V to (+VS + 300mV) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
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ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
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PIN DESCRIPTIONS PIN CONFIGURATION Top View SO PIN DESIGNATOR GND B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 DNC DNC GND +VS CLK +VS OE Bit 7 8 21 REFB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Bit 8 9 20 +VS 19 MSBI Bit 9 10 19 MSBI Bit 10 (LSB) 11 18 OE 20 21 +VS REFB DNC 12 17 +VS DNC 13 16 CLK 22 CM GND 14 15 +VS 23 REFT 24 25 26 27 28 +VS GND IN IN GND GND 1 28 GND Bit 1(MSB) 2 27 IN Bit 2 3 26 IN Bit 3 4 25 GND Bit 4 5 24 +VS Bit 5 6 23 REFT B
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TYPICAL CHARACTERISTICS At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 500kHz fS = 10MHz fIN = 4.8MHz –20 –40 Amplitude (dB) Amplitude (dB) –20 –60 –80 –100 –40 –60 –80 –100 –120 –120 0 1.0 2.0 3.0 4.0 5.0 0 2.0 4.0 Frequency (MHz) 6.0 SPECTRAL PERFORMANCE 0 fIN = 9.8MHz f1 = 4.5MHz –20 –20 –40 Amplitude (dB) Amplitude (dB) 10.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. SWEPT POWER SFDR DYNAMIC PERFORMANCE vs INPUT FREQUENCY 100 85 fIN = 10MHz 80 80 75 SFDR (dBFS) SFDR, SNR (dB) SFDR 70 65 SNR 60 40 20 60 55 100k 0 1M 10M –50 100M –40 –30 –20 –10 0 10 Input Amplitude (dBm) Frequency (Hz) SWEPT POWER SNR INTEGRAL LINEARITY ERROR 60 4.0 fIN = 500kHz fIN = 10MHz 50 2.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. SPURIOUS-FREE DYNAMIC RANGE vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 0.3 90 fIN = 500kHz 80 0.2 SFDR (dBFS) DLE (LSB) fIN = 10MHz 0.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted. GAIN ERROR vs TEMPERATURE OFFSET ERROR vs TEMPERATURE –1.75 Offset (% FSR) Gain (% FSR) –0.05 –0.55 –1.05 –1.55 –2.0 –2.25 –2.50 –50 –25 0 25 50 75 100 –50 –25 0 Temperature (°C) 0 1M –1 0.8M Counts Track-Mode Input Response (dB) 1.2M –2 0.4M –4 0.2M –5 1M 10M 100M 0.0 N–2 1G Frequency (Hz) 8 75 100 0.
PAGE 9
THEORY OF OPERATION Op Amp Bias The ADS820 is a high-speed, sampling A/D converter with pipelining. It uses a fully differential architecture and digital error correction to ensure 10-bit resolution. The differential track-and-hold circuit is shown in Figure 1. The switches are controlled by an internal clock that has a non-overlapping, two-phase signal, φ1 and φ2. At the sampling time the input signal is sampled on the bottom plates of the input capacitors.
PAGE 10
time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error correction circuit that can adjust the output data based on the information found on the redundant bits. This technique gives the ADS820 excellent differential linearity and ensures no missing codes at the 10-bit level. There is a 6.5 clock cycle data latency from the start convert signal to the valid output data.
PAGE 11
AC performance. It is important to select a transformer that gives low distortion and does not exhibit core saturation at full-scale voltage levels. Since the transformer does not appreciably load the ladder, there is no need to buffer the CM output in this instance. In general, it is advisable to keep the current draw from the CM output pin below 0.5µA to avoid nonlinearity in the internal reference ladder.
PAGE 12
+5V 604Ω +5V 301Ω BAS16(1) (3) Optional High Impedance Input Amplifier 301Ω 301Ω 27 IN OPA842 2.49kΩ 0.1µF 22pF +5V(2) 0.1µF –5V DC-Coupled Input Signal 604Ω +5V ADS820 (3) OPA842 604Ω 49.9Ω OPA130 +5V –5V 24.9Ω 2.49kΩ +2.25V 22 CM +5V 301Ω BAS16(1) (3) Input Level Shift Buffer 301Ω 26 IN OPA842 0.1µF –5V 22pF 604Ω NOTES: (1) A Philips BAS16 diode or equivalent may be used. (2) Supply bypassing not shown. (3) OPA620 or OPA650 may be substituted.
PAGE 13
The ADS820 can also be configured with a single-ended input full-scale range of +0.25V to +4.25V by tying the complementary input to the common-mode reference voltage, as shown in Figure 8. This configuration will result in increased evenorder harmonics, especially at higher input frequencies. However, this trade-off may be quite acceptable for time-domain applications. The driving amplifier must give adequate performance with a +0.25V to +4.25V output swing in this case.
PAGE 14
PC-BOARD LAYOUT AND BYPASSING A well-designed, clean PC-board layout will assure proper operation and clean spectral response. Proper grounding and bypassing, short lead lengths, and the use of ground planes are particularly important for high frequency circuits. Multilayer PC boards are recommended for best performance but if carefully designed, a two-sided pc board with large, heavy ground planes can give excellent results.
PAGE 15
FIGURE 10. ADS820 Interface Schematic with AC-Coupling and External Buffers. ADS820 SBAS037B www.ti.com 15 R2 50Ω AC Input Signal Mini-Circuits TT1-6-KK81 or equivalent 0.1µF 0.1µF Ext Clk 22pF R1 50Ω 22pF (1) 0.
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PACKAGE OPTION ADDENDUM www.ti.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.