Datasheet

ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010 www.ti.com
TIMING REQUIREMENTS (see Figure 45, Figure 46, Figure 47, and Figure 48) (continued)
All specifications typical at –40°C to 125°C, +VA = 2.7 V to 5.25 V (unless otherwise specified)
PARAMETER TEST CONDITIONS
(1) (2)
MIN TYP MAX UNIT
+VBD = 1.8 V 38
t
d1
Delay time, CS low to first data (DO–15) out +VBD = 3 V 27 ns
+VBD = 5 V 17
+VBD = 1.8 V 8
t
su1
Setup time, CS low to first rising edge of SCLK +VBD = 3 V 6 ns
+VBD = 5 V 4
+VBD = 1.8 V 35
t
d2
Delay time, SCLK falling to SDO next data bit valid +VBD = 3 V 27 ns
+VBD = 5 V 17
+VBD = 1.8 V 7
t
h1
Hold time, SCLK falling to SDO data bit valid +VBD = 3 V 5 ns
+VBD = 5 V 3
+VBD = 1.8 V 26
t
d3
Delay time, 16
th
SCLK falling edge to SDO 3-state +VBD = 3 V 22 ns
+VBD = 5 V 13
+VBD = 1.8 V 2
t
su2
Setup time, SDI valid to rising edge of SCLK +VBD = 3 V 3 ns
+VBD = 5 V 4
+VBD = 1.8 V 12
t
h2
Hold time, rising edge of SCLK to SDI valid +VBD = 3 V 10 ns
+VBD = 5 V 6
+VBD = 1.8 V 20
t
w1
Pulse duration CS high +VBD = 3 V 20 ns
+VBD = 5 V 20
+VBD = 1.8 V 24
t
d4
Delay time CS high to SDO 3-state +VBD = 3 V 21 ns
+VBD = 5 V 12
+VBD = 1.8 V 20
t
wh
Pulse duration SCLK high +VBD = 3 V 20 ns
+VBD = 5 V 20
+VBD = 1.8 V 20
t
wl
Pulse duration SCLK low +VBD = 3 V 20 ns
+VBD = 5 V 20
+VBD = 1.8 V 20
Frequency SCLK +VBD = 3 V 20 MHz
+VBD = 5 V 20
10 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961