Datasheet

MXO AINP
Ch0
Chn*
Ch2
Ch1
ADC
GPIO0,H Alarm
GPIO1,L Alarm
SDI
GPIO2,Range
SCLK
CS
SDO
To
Host
REF
10 Fm
REF5025
o/p
Fromsensors,INA etc.
Thereisarestrictionon
sourceimpedance.
R 50
SOURCE
£ W
GPIO3, PD
ADS7950, ADS7951, ADS7952, ADS7953
ADS7954, ADS7955, ADS7956, ADS7957
ADS7958, ADS7959, ADS7960, ADS7961
SLAS605A –JUNE 2008–REVISED JANUARY 2010 www.ti.com
APPLICATION INFORMATION
ANALOG INPUT
The ADS79XX device family offers 12/10/8-bit ADCSs with 16/12/8/4 channel multiplexers for analog input. The
multiplexer output is available on the MXO pin. AINP is the ADC input pin. The devices offers flexibility for a
system designer as both signals are accessible esternally.
Typically it is convenient to short MXO to the AINP pin so that signal input to each multiplexer channel can be
processed independently. In this condition it is recommended to limit source impedance to 50Ω or less. Higher
source impedance may affect the signal settling time after a multiplexer channel change. This condition can
affect linearity and total harmonic distortion.
GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all
references related to 'GPIO 0' only are valid in case of QFN package devices.
Figure 57. Typical Application Diagram Showing MXO Shorted to AINP
Another option is to add a common ADC driver buffer between the MXO and AINP pins. This relaxes the
restriction on source impedance to a large extent. Refer to the typical characteristics section for the effect of
source impedance on device performance. The typical characteristics show that the device has respectable
performance with up to 1kΩ source impedance. This topology (including a common ADC driver) is useful when
all channel signals are within the acceptable range of the ADC. In this case the user can save on signal
conditioning circuit for each channel.
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Product Folder Link(s): ADS7950, ADS7951, ADS7952, ADS7953 ADS7954, ADS7955, ADS7956, ADS7957 ADS7958,
ADS7959, ADS7960, ADS7961