Datasheet

ADS7834
8
SBAS098A
www.ti.com
internal reference. This reference can be used to supply a
small amount of source current to an external load, but the
load should be static. Due to the internal 10kΩ resistor, a
dynamic load will cause variations in the reference voltage,
and will dramatically affect the conversion result. Note that
even a static load will reduce the internal reference voltage
seen at the buffer input. The amount of reduction depends on
the load and the actual value of the internal “10kΩ” resistor.
The value of this resistor can vary by ±30%.
The V
REF
pin should be bypassed with a 0.1µF capacitor
placed as close as possible to the ADS7834 package. In
addition, a 2.2µF tantalum capacitor should be used in
parallel with the ceramic capacitor. Placement of this ca-
pacitor, while not critical to performance, should be placed
as close to the package as possible.
EXTERNAL REFERENCE
The internal reference is connected to the V
REF
pin and to the
internal buffer via a 10kΩ series resistor. Thus, the reference
voltage can easily be overdriven by an external reference
voltage. The voltage range for the external voltage is 2.0V
to 2.55V, corresponding to an analog input range of 2.0V to
2.55V.
While the external reference will not source significant
current into the V
REF
pin, it does have to drive the series
10kΩ resistor that is terminated into the 2.5V internal
reference (the exact value of the resistor will vary up to
±30% from part to part). In addition, the V
REF
pin should
still be bypassed to ground with at least a 0.1µF ceramic
capacitor (placed as close to the ADS7834 as possible). The
reference will have to be stable with this capacitive load.
Depending on the particular reference and A/D conversion
speed, additional bypass capacitance may be required, such
as the 2.2µF tantalum capacitor shown in Figure 1.
Reasons for choosing an external reference over the internal
reference vary, but there are two main reasons. One is to
achieve a given input range. For example, a 2.048V refer-
ence provides for a 0V to 2.048V input range—or 500µV
per LSB. The other is to provide greater stability over
temperature. (The internal reference is typically 20ppm/°C
which translates into a full-scale drift of roughly 1 output
code for every 12°C. This does not take into account other
sources of full-scale drift). If greater stability over tempera-
ture is needed, then an external reference with lower tem-
perature drift will be required.
DIGITAL INTERFACE
Figure 2 shows the serial data timing and Figure 3 shows the
basic conversion timing for the ADS7834. The specific
timing numbers are listed in Table I. There are several
important items in Figure 3 which give the converter addi-
tional capabilities over typical 8-pin converters. First, the
transition from sample mode to hold mode is synchronous to
the falling edge of CONV and is not dependent on CLK.
Second, the CLK input is not required to be continuous
during the sample mode. After the conversion is complete,
the CLK may be kept LOW or HIGH.
FIGURE 2. Serial Data and Clock Timing.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
ACQ
Acquisition Time 350 ns
t
CONV
Conversion Time 1.625 µs
t
CKP
Clock Period 125 5000 ns
t
CKL
Clock LOW 50 ns
t
CKH
Clock HIGH 50 ns
t
CKDH
Clock Falling to Current Data 5 15 ns
Bit No Longer Valid
t
CKDS
Clock Falling to Next Data Valid 30 50 ns
t
CVL
CONV LOW 40 ns
t
CVH
CONV HIGH 40 ns
t
CKCH
CONV Hold after Clock Falls
(1)
10 ns
t
CKCS
CONV Setup to Clock Falling
(1)
10 ns
t
CKDE
Clock Falling to DATA Enabled 20 50 ns
t
CKDD
Clock Falling to DATA 70 100 ns
High Impedance
t
CKSP
Clock Falling to Sample Mode 5 ns
t
CKPD
Clock Falling to Power-Down Mode 50 ns
t
CVHD
CONV Falling to Hold Mode 5 ns
(Aperture Delay)
t
CVSP
CONV Rising to Sample Mode 5 ns
t
CVPU
CONV Rising to Full Power-up 50 ns
t
CVDD
CONV Changing State to DATA 70 100 ns
High Impedance
t
CVPD
CONV Changing State to 50 ns
Power-Down Mode
t
DRP
CONV Falling to Start of CLK 5 µs
(for hold droop < 0.1 LSB)
Note: (1) This timing is not required under some situations. See text for more information.
TABLE I. Timing Specifications (T
A
= –40°C to +85°C,
C
LOAD
= 30pF).
The asynchronous nature of CONV to CLK raises some
interesting possibilities, but also some design consider-
ations. Figure 3 shows that CONV has timing restraints in
relation to CLK (t
CKCH
and t
CKCS
). However, if these times
are violated (which could happen if CONV is completely
asynchronous to CLK), the converter will perform a conver-
sion correctly, but the exact timing of the conversion is
indeterminate. Since the setup and hold time between CONV
and CLK has been violated in this example, the start of
conversion could vary by one clock cycle. (Note that the
start of conversion can be detected by using a pull-up
resistor on DATA. When DATA drops out of high-imped-
ance and goes LOW, the conversion has started and that
clock cycle is the first of the conversion.)
In addition if CONV is completely asynchronous to CLK
and CLK is continuous, then there is the possibility that
CLK will transition just prior to CONV going LOW. If this
DATA
CLK
t
CKH
t
CKP
t
CKDH
t
CKDS
t
CKL