Datasheet

ADS7830
SBAS302C –DECEMBER 2003–REVISED OCTOBER 2012 www.ti.com
DIGITAL INTERFACE A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
The ADS7830 supports the I2C serial bus and data
way that the SDA line is stable LOW during the HIGH
transmission protocol, in all three defined modes:
period of the acknowledge clock pulse. Of course,
standard, fast, and high-speed. A device that sends
setup and hold times must be taken into account. A
data onto the bus is defined as a transmitter, and a
master must signal an end of data to the slave by not
device receiving data as a receiver. The device that
generating an acknowledge bit on the last byte that
controls the message is called a “master.” The
has been clocked out of the slave. In this case, the
devices that are controlled by the master are “slaves.”
slave must leave the data line HIGH to enable the
The bus must be controlled by a master device that
master to generate the STOP condition.
generates the serial clock (SCL), controls the bus
access, and generates the START and STOP Figure 14 details how data transfer is accomplished
conditions. The ADS7830 operates as a slave on the on the I
2
C bus. Depending upon the state of the R/W
I
2
C bus. Connections to the bus are made via the bit, two types of data transfer are possible:
open-drain I/O lines SDA and SCL.
1. Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
The following bus protocol has been defined (as
master is the slave address. Next follows a
shown in Figure 14):
number of data bytes. The slave returns an
• Data transfer may be initiated only when the bus
acknowledge bit after the slave address and each
is not busy.
received byte.
• During data transfer, the data line must remain
2. Data transfer from a slave transmitter to a
stable whenever the clock line is HIGH. Changes
master receiver. The first byte, the slave
in the data line while the clock line is HIGH will be
address, is transmitted by the master. The slave
interpreted as control signals.
then returns an acknowledge bit. Next, a number
Accordingly, the following bus conditions have been
of data bytes are transmitted by the slave to the
defined:
master. The master returns an acknowledge bit
after all received bytes other than the last byte. At
Bus Not Busy: Both data and clock lines remain
the end of the last received byte, a not-
HIGH.
acknowledge is returned.
Start Data Transfer: A change in the state of the
The master device generates all of the serial clock
data line, from HIGH to LOW, while the clock is
pulses and the START and STOP conditions. A
HIGH, defines a START condition.
transfer is ended with a STOP condition or a
repeated START condition. Since a repeated START
Stop Data Transfer: A change in the state of the
condition is also the beginning of the next serial
data line, from LOW to HIGH, while the clock line is
transfer, the bus will not be released.
HIGH, defines the STOP condition.
The ADS7830 may operate in the following two
Data Valid: The state of the data line represents valid
modes:
data, when, after a START condition, the data line is
stable for the duration of the HIGH period of the clock
• Slave Receiver Mode: Serial data and clock are
signal. There is one clock pulse per bit of data.
received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted.
Each data transfer is initiated with a START condition
START and STOP conditions are recognized as
and terminated with a STOP condition. The number
the beginning and end of a serial transfer.
of data bytes transferred between START and STOP
Address recognition is performed by hardware
conditions is not limited and is determined by the
after reception of the slave address and direction
master device. The information is transferred byte-
bit.
wise and each receiver acknowledges with a ninth-bit.
• Slave Transmitter Mode: The first byte (the slave
Within the I
2
C bus specifications a standard mode
address) is received and handled as in the slave
(100kHz clock rate), a fast mode (400kHz clock rate),
receiver mode. However, in this mode the
and a highspeed mode (3.4MHz clock rate) are
direction bit will indicate that the transfer direction
defined. The ADS7830 works in all three modes.
is reversed. Serial data is transmitted on SDA by
the ADS7830 while the serial clock is input on
Acknowledge: Each receiving device, when
SCL. START and STOP conditions are
addressed, is obliged to generate an acknowledge
recognized as the beginning and end of a serial
after the reception of each byte. The master device
transfer.
must generate an extra clock pulse that is associated
with this acknowledge bit.
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