Datasheet

CONVST
BUSY
CONVERSION1 CONVERSION2 CONVERSION3
S1= ‘0’
CONVERSION1 CONVERSION2 CONVERSION 3
S1= ‘1’,S0= ‘0’ (half-clockmodeonly)
CONVERSION1 CONVERSION2 CONVERSION3
S1= ‘1’,S0= ‘1’ (half-clockmodeonly)
CONVST
BUSY
CONVST
BUSY
ADS8363
ADS7263
ADS7223
www.ti.com SBAS523B –OCTOBER 2010–REVISED JANUARY 2011
Bits[3:2] SP[1:0]—Sequence position bits (read only).
These bits indicate the setting of the pseudo-differential input multiplexer in sequencer mode.
00 = Inputs selected using bits C1[1:0] are converted with next rising edge of CONVST (default).
01 = Inputs selected using bits C2[1:0] are converted with next rising edge of CONVST.
10 = Inputs selected using bits C3[1:0] are converted with next rising edge of CONVST.
11 = Inputs selected using bits C4[1:0] are converted with next rising edge of CONVST.
Bits [1:0] FD[1:0]—FIFO depth control (see Figure 33).
These bits control the depth of the internal FIFO if CONFIG register bit FE = '1'.
00 = One conversion result per channel is stored in the FIFO for burst read access (default).
01 = Two conversion results per channel are stored in the FIFO for burst read access.
10 = Three conversion results per channel are stored in the FIFO for burst read access.
11 = Four conversion results per channel are stored in the FIFO for burst read access .
Figure 32. Sequencer Modes
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