Datasheet

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DIGITAL CHARACTERISTICS
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)
Typical values are at 25 ° C, min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, 50% clock duty cycle, – 1dBFS differential analog input, internal reference
mode (unless otherwise noted).
ADS6424 ADS6423 ADS6422
F
s
= 105 MSPS F
s
= 80 MSPS F
s
= 65 MSPS
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Near channel 92 94 100
Cross-talk signal frequency
= 10 MHz
Cross-talk dBc
Far channel 105 106 108
Cross-talk signal frequency
= 10 MHz
Recovery to within 1% (of 1 1 1
Input overload Clock
final value) for 6-dB overload
recovery cycles
with sine wave input
AC PSRR 35 35 35
< 100 MHz signal, 100 mV
PP
Power Supply dBc
on AVDD supply
Rejection Ratio
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 AVDD = LVDD = 3.3V, I
O
= 3.5mA, R
LOAD
= 100 Ω
(1)
.
All LVDS specifications are characterized, but not tested at production.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS
High-level input voltage 2.4 V
Low-level input voltage 0.8 V
High-level input current 10 μ A
Low-level input current 10 μ A
Input capacitance 4 pF
DIGITAL OUTPUTS
High-level output voltage 1375 mV
Low-level output voltage 1025 mV
|V
OD
| Output differential voltage 250 350 450 mV
V
OS
Output offset voltage Common-mode voltage of OUTP and OUTM 1200 mV
Output capacitance Output capacitance inside the device, from either output to ground 2 pF
(1) I
O
refers to the LVDS buffer current setting, R
LOAD
is the external differential load resistance between the LVDS output pair.
Copyright © 2007, Texas Instruments Incorporated 9
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