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DESCRIPTION OF PARALLEL PINS

ADS6424

ADS6423

ADS6422

SLAS532A – MAY 2007 – REVISED JUNE 2007

Table 5. SCLK, SDATA Control Pins

SCLK SDATA DESCRIPTION

LOW LOW NORMAL conversion.

SYNC - ADC outputs sync pattern on all channels. This pattern can be used by the receiver to align the

LOW HIGH

deserialized data to the frame boundary. See Capture Test Patterns for details.

POWER DOWN – Global power down, all channels of the ADC are powered down, including internal references,

HIGH LOW

PLL and output buffers.

DESKEW - ADC outputs deskew pattern on all channels. This pattern can be used by the receiver to ensure

HIGH HIGH

deserializer uses the right clock edge. See Capture Test Patterns for details.

Table 6. SEN Control Pin

SEN DESCRIPTION

0 External reference and 0 dB coarse gain (full-scale = 2 V

)

(3/8)LVDD External reference and 3.5 dB coarse gain (full-scale = 1.34 V

)

(5/8)LVDD Internal reference and 3.5 dB coarse gain (full-scale = 1.34 V

)

LVDD Internal reference and 0 dB coarse gain (full-scale = 2 V

)

Independent of the programming mode used, after power-up the parallel pins PDN, CFG1 to CFG4 will

automatically configure the device as per the voltage applied (refer to Table 7 to Table 11 ).

Table 7. PDN Control Pin

PDN DESCRIPTION

0 Normal operation

AVDD Power down global

Table 8. CFG1 Control Pin

CFG1 DESCRIPTION

0 DDR Bit clock and 1-wire interface

(3/8)LVDD Not used

(5/8)LVDD SDR Bit clock and 2-wire interface

LVDD DDR Bit clock and 2-wire interface

Table 9. CFG2 Control Pin

CFG2 DESCRIPTION

0 12x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)

(3/8)LVDD 14x Serialization and capture at falling edge of bit clock (only in 2-wire SDR bit clock mode)

(5/8)LVDD 14x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)

LVDD 12x Serialization and capture at rising edge of bit clock (only in 2-wire SDR bit clock mode)

Table 10. CFG3 Control Pin

CFG3 RESERVED - TIE TO GROUND

Table 11. CFG4 Control Pin

CFG4 DESCRIPTION

0 MSB First and 2s complement

(3/8)LVDD MSB First and offset binary

(5/8)LVDD LSB First and offset binary

LVDD LSB First and 2s complement

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