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DCLKP
DCLKM
CLKM
CLKP
FCLKM
FCLKP
DOP
DOM
Sample N–1
t
A
t
PD_CLK
Sample
N
Sample
N+11
Sample
N+12
Sample
N+13
Input
Signal
Input
Clock
Bit
Clock
Output
Data
Frame
Clock
D11 D11D7 D7D3 D3D9 D9D5 D5D1 D1D10 D10D6 D6D2 D2D8 D8D4 D4D0 D0
Latency 12 Clocks
Sample N
T0105-03
ADS6424
ADS6423
ADS6422
SLAS532A – MAY 2007 – REVISED JUNE 2007
TIMING SPECIFICATIONS (continued)
Typical values are at 25 ° C, min and max values are across the full temperature range T
MIN
= – 40 ° C to T
MAX
= 85 ° C, AVDD =
LVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 V
PP
clock amplitude, C
L
= 5 pF , I
O
= 3.5 mA,
R
L
= 100 Ω , no internal termination, unless otherwise noted.
ADS6424 ADS6423 ADS6422
TEST
F
s
= 105 MSPS F
s
= 80 MSPS F
s
= 65 MSPS
PARAMETER UNIT
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Bit clock and
From – 100 mV to
t
RISE
Frame clock rise 50 100 200 50 100 200 50 100 200 ps
+100 mV
time
Bit clock and
From +100 mV to
t
FALL
Frame clock fall 50 100 200 50 100 200 50 100 200 ps
– 100 mV
time
Bit clock duty
45% 50% 55% 45% 50% 55% 45% 50% 55%
cycle
Frame clock duty
47% 50% 53% 47% 50% 53% 47% 50% 53%
cycle
Figure 1. Latency
Copyright © 2007, Texas Instruments Incorporated 11
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