Datasheet

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Output Data Format
Output Timings
ADS6125, ADS6124
ADS6123, ADS6122
SLAS560A – OCTOBER 2007 – REVISED MARCH 2008
Figure 104. LVDS Eye Diagram - No Internal Termination Figure 105. LVDS Eye Diagram with 100- Ω Internal
5-pF Load Capacitance Termination
Blue Trace - Output Clock (CLKOUT) 10-pF Load Capacitance
Pink Trace - Output Data Blue Trace - Output Clock (CLKOUT)
Pink Trace - Output Data
Two output data formats are supported – 2s complement and offset binary. They can be selected using the
parallel control pin SEN or the serial interface register bit <DATA FORMAT> (see Table 8 ).
The following table lists the timings at lower sampling frequencies.
Table 17. Timing Characteristics at Lower Sampling Frequencies
(1) (2)
t
su
DATA SETUP TIME, ns t
h
DATA HOLD TIME, ns t
PDI
CLOCK PROPAGATION DELAY, ns
Fs, MSPS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
CMOS INTERFACE, DRVDD = 2.5 V to 3.3 V
40 11.3 12.8 10 11.2 5 6.5 7.9
20 23 25 21 23
10 48 50 46 48
DDR LVDS INTERFACE, DRVDD = 3.3 V
40 10.2 10.8 0.7 1.7 4.3 5.8 7.3
20 22 23 0.7 1.7 4.5 6.5 8.5
10 47 48 0.7 1.7 4.5 6.5 8.5
(1) Timing parameters are specified by design and characterization and not tested in production.
(2) Timings are specified with default output buffer drive strength and C
L
= 5 pF
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Product Folder Link(s): ADS6125, ADS6124 ADS6123, ADS6122