Datasheet

®
ADS574
6
THEORY OF OPERATION
In the ADS574, the advantages of advanced CMOS technol-
ogy—high logic density, stable capacitors, precision analog
switches—and Burr-Brown’s state of the art laser trimming
techniques are combined to produce a fast, low power
analog-to-digital converter with internal sample/hold.
The charge-redistribution successive-approximation circuitry
converts analog input voltages into digital words.
A simple example of a charge-redistribution A/D converter
with only 3 bits is shown in Figure 1.
approximation is made by connecting S
2
to the reference and
S
3
to GND, and latching S
2
according to the output of the
comparator. After three successive approximation steps have
been made the voltage level at the comparator will be within
1/2LSB of GND, and a digital word which represents the
analog input can be determined from the positions of S
1
, S
2
and S
3
.
OPERATION
BASIC OPERATION
Figure 2 shows the minimum circuit required to operate the
ADS574 in a basic ±10V range in the Control Mode (dis-
cussed in detail in a later section.) The falling edge of a
Convert Command (a pulse taking pin 5 LOW for a mini-
mum of 25ns) both switches the ADS574 input to the hold
state and initiates the conversion. Pin 28 (STATUS) will
output a HIGH during the conversion, and falls only after the
conversion is completed and the data has been latched on the
data output pins (pins 16 to 27.) Thus, the falling edge of
STATUS on pin 28 can be used to read the data from the
conversion. Also, during conversion, the STATUS signal
puts the data output pins in a High-Z state and inhibits the
input lines. This means that pulses on pin 5 are ignored, so
that new conversions cannot be initiated during the conver-
sion, either as a result of spurious signals or to short-cycle
the ADS574.
The ADS574 will begin acquiring a new sample as soon as
the conversion is completed, even before the STATUS
output falls, and will track the input signal until the next
conversion is started. The ADS574 is designed to complete
a conversion and accurately acquire a new signal in 25µs
max over the full operating temperature range, so that
conversions can take place at a full 40kHz.
CONTROLLING THE ADS574
The Burr-Brown ADS574 can be easily interfaced to most
microprocessor systems and other digital systems. The
microprocessor may take full control of each conversion, or
the converter may operate in a stand-alone mode, controlled
only by the R/C input. Full control consists of selecting an
8- or 12-bit conversion cycle, initiating the conversion, and
reading the output data when ready—choosing either 12 bits
all at once, or the 8 MSB bits followed by the 4 LSB bits in
a left-justified format. The five control inputs (12/8, CS, A
0
,
R/C, and CE) are all TTL/CMOS-compatible. The functions
of the control inputs are described in Table II. The control
function truth table is shown in Table III.
STAND-ALONE OPERATION
For stand-alone operation, control of the converter is accom-
plished by a single control line connected to R/C. In this
mode CS and A
0
are connected to digital common and CE
and 12/8 are connected to +5V. The output data are pre-
sented as 12-bit words. The stand-alone mode is used in
systems containing dedicated input ports which do not
require full bus interface capability.
FIGURE 1. 3-Bit Charge Redistribution A/D.
INPUT SCALING
Precision laser-trimmed scaling resistors at the input divide
standard input ranges (0V to +10V, 0V to +20V, ±5V or
±10V) into levels compatible with the CMOS characteristics
of the internal capacitor array.
SAMPLING
While sampling, the capacitor array switch for the MSB
capacitor (S
1
) is in position “S”, so that the charge on the
MSB capacitor is proportional to the voltage level of the
analog input signal. The remaining array switches (S
2
and
S
3
) are set to position “G”. Switch S
C
is closed, setting the
comparator input offset to zero.
CONVERSION
When a conversion command is received, switch S
1
is opened
to trap a charge on the MSB capacitor proportional to the
analog input level at the time of the sampling command, and
switch S
C
is opened to float the comparator input. The charge
trapped in the capacitor array can now be moved between the
three capacitors in the array by connecting switches S
1
, S
2
, and
S
3
to positions “R” (to connect to the reference) or “G” (to
connect to GND), thus changing the voltage generated at the
comparator input.
During the first approximation, the MSB capacitor is con-
nected through switch S
1
to the reference, while switches S
2
and S
3
are connected to GND. Depending on whether the
comparator output is HIGH or LOW, the logic will then
latch S
1
in position “R” or “G”. Similarly, the second
C
R
G
2C
R
G
4C
R
G
+
–
S
3
S
2
S
1
S
C
Comparator
L
o
g
i
c
Reference
Input
S
Signal
Analog
Input
Out