Datasheet

PD
Device Fully
Powers Down
Device Fully
Powers Up
500
µ
s
1
µ
s
NOTE: The shown power−up time is based on 1
µ
F bypass capacitors on the reference pins.
See the Theory of Operation section for details.
SERIAL INTERFACE TIMING
Start Sequence
t
1
t
7
t
6
D7
(MSB)
D6 D5 D4 D3 D2 D1 D0
t
2
t
3
t
4
t
5
ADCLK
CS
SCLK
SDATA
Outputs change on
next rising clock edge
after CS goes high.
Data latched on
each rising edge of SCLK.
NOTE: Data is shifted in MSB first.
ADS5270
www.ti.com ............................................................................................................................................... SBAS293F – JANUARY 2004 – REVISED JANUARY 2009
LVDS TIMING DIAGRAM (PER ADC CHANNEL) (continued)
POWER-DOWN TIMING
PARAMETER DESCRIPTION MIN TYP MAX UNIT
t
1
Serial CLK Period 50 ns
t
2
Serial CLK High Time 20 ns
t
3
Serial CLK Low Time 20 ns
t
4
Data Setup Time 5 ns
t
5
Data Hold Time 5 ns
t
6
CS Fall to SCLK Rise 8 ns
t
7
SCLK Rise to CS Rise 8 ns
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