Datasheet

ADS1294, ADS1294R
ADS1296, ADS1296R
ADS1298, ADS1298R
SBAS459I –JANUARY 2010–REVISED JANUARY 2012 www.ti.com
LOFF_STATN (Read-Only Register)
Address = 13h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
IN8N_OFF IN7N_OFF IN6N_OFF IN5N_OFF IN4N_OFF IN3N_OFF IN2N_OFF IN1N_OFF
This register stores the status of whether the negative electrode on each channel is on or off. See the Lead-Off
Detection subsection of the ECG-Specific Functions section for details. Ignore the LOFF_STATN values if the
corresponding LOFF_SENSN bits are not set to '1'.
'0' is lead-on (default) and '1' is lead-off. When the LOFF_SENSEN bits are '0', the LOFF_STATP bits should be
ignored.
GPIO: General-Purpose I/O Register
Address = 14h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1
The General-Purpose I/O Register controls the action of the three GPIO pins. Note that when RESP_CTRL[1:0]
is in mode 01 and 11, the GPIO2, GPIO3, and GPIO4 pins are not available for use.
Bits[7:4] GPIOD[4:1]: GPIO data
These bits are used to read and write data to the GPIO ports.
When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are
programmed as inputs or as outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the
GPIOD has no effect. GPIO is not available in certain respiration modes.
Bits[3:0] GPIOC[4:1]: GPIO control (corresponding GPIOD)
These bits determine if the corresponding GPIOD pin is an input or output.
0 = Output
1 = Input (default)
PACE: PACE Detect Register
Address = 15h
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 PACEE1 PACEE0 PACEO1 PACEO0 PD_PACE
This register provides the PACE controls that configure the channel signal used to feed the external PACE detect
circuitry. See the Pace Detect subsection of the ECG-Specific Functions section for details.
Bits[7:5] Must always be set to '0'
Bits[4:3] PACEE[1:0]: PACE even channels
These bits control the selection of the even number channels available on TEST_PACE_OUT1. Note that only one channel
may be selected at any time.
00 = Channel 2 (default)
01 = Channel 4
10 = Channel 6, ADS1296/8/6R/8R only
11 = Channel 8, ADS1298/8R only
Bits[2:1] PACEO[1:0]: PACE odd channels
These bits control the selection of the odd number channels available on TEST_PACE_OUT2. Note that only one channel
may be selected at any time.
00 = Channel 1 (default)
01 = Channel 3
10 = Channel 5, ADS1296/8/6R/8R only
11 = Channel 7, ADS1298/8R only
Bit 0 PD_PACE: PACE detect buffer
This bit is used to enable/disable the PACE detect buffer.
0 = PACE detect buffer turned off (default)
1 = PACE detect buffer turned on
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Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R