Datasheet

ADS1210, ADS1211
18
SBAS034B
www.ti.com
ADS1210
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
XTAL
C
1
12pF
DV
DD
GND
DGND
DGND
DGND
R
1
3kΩ
R
2
3kΩ
R
4
1kΩ
R
3
1kΩ
C
2
12pF
±10V
±10V
AV
DD
AGND
DV
DD
1.0µF
FIGURE 12. ±10V Input Configuration Using V
BIAS
.
The circuitry which generates the +2.5V reference can be
disabled via the Command Register and will result in a lower
power dissipation. The reference circuitry consumes a little over
1.6mA of current with no external load. When the ADS1210/11
is in its default state, the internal reference is enabled.
V
BIAS
The V
BIAS
output voltage is dependent on the reference input
(REF
IN
) voltage and is approximately 1.33 times as great.
This output is used to bias input signals such that bipolar
signals with spans of greater than 5V can be scaled to match
the input range of the ADS1210/11. Figure 12 shows a
connection diagram which will allow the ADS1210/11 to
accept a ±10V input signal (40V full-scale range).
This method of scaling and offsetting the ±20V differential
input signal will be a concern for those requiring minimum
power dissipation. V
BIAS
will supply 1.68mA for every chan-
nel connected as shown. For the ADS1211, the current draw
is within the specifications for V
BIAS
, but, at 12mW, the
power dissipation is significant. If this is a concern, resistors
R
1
and R
2
can be set to 9kΩ and R
3
and R
4
to 3kΩ. This will
reduce power dissipation by one-third. In addition, these
resistors can also be set to values which will provide any
arbitrary input range. In all cases, the maximum current into
or out of V
BIAS
should not exceed its specification of 10mA.
Note that the connection diagram shown in Figure 12 causes
a constant amount of current to be sourced by V
BIAS
. This
will be very important in higher resolution designs as the
voltage at V
BIAS
will not change with loading, as the load is
constant. However, if the input signal is single-ended and one
side of the input is grounded, the load will not be constant and
V
BIAS
will change slightly with the input signal. Also, in all
cases, note that noise on V
BIAS
introduces a common-mode
error signal which is rejected by the converter.
The 3k resistors should not be used as part of an anti-alias
filter with a capacitor across the inputs. The ADS1210
samples charge from the capacitor which has the effect of
introducing an offset in the measurement. This might be
acceptable for relative differential measurements.
The circuitry to generate V
BIAS
is disabled when the
ADS1210/11 is in its default state, and it must be enabled,
via the Command Register, in order for the V
BIAS
voltage to
be present. When enabled, the V
BIAS
circuitry consumes
approximately 1mA with no external load.
On power-up, external signals may be present before V
BIAS
is enabled. This can create a situation in which a negative
voltage is applied to the analog inputs (–2.5V for the circuit
shown in Figure 12), reverse biasing the negative input
protection diode. This situation should not be a problem as
long as the resistors R
1
and R
2
limit the current being
sourced by each analog input to under 10mA (a potential of
0V at the analog input pin should be used in the calculation).
DIGITAL OPERATION
SYSTEM CONFIGURATION
The Micro Controller (MC) consists of an ALU and a
register bank. The MC has two states: power-on reset and
convert. In the power-on reset state, the MC resets all the
registers to their default state, sets up the modulator to a
stable state, and performs self-calibration at a 850Hz data
rate. After this, it enters the convert mode, which is the
normal mode of operation for the ADS1210/11.
The ADS1210/11 has 5 internal registers, as shown in Table
VII. Two of these, the Instruction Register and the Com-
mand Register, control the operation of the converter. The
Data Output Register (DOR) contains the result from the
most recent conversion. The Offset and Full-Scale Calibra-
tion Registers (OCR and FCR) contain data used for correct-
ing the internal conversion result before it is placed into the
DOR. The data in these two registers may be the result of a
calibration routine, or they may be values which have been
written directly via the serial interface.
TABLE VII. ADS1210/11 Registers.
INSR Instruction Register 8 Bits
DOR Data Output Register 24 Bits
CMR Command Register 32 Bits
OCR Offset Calibration Register 24 Bits
FCR Full-Scale Calibration Register 24 Bits
Communication with the ADS1210/11 is controlled via the
Instruction Register (INSR). Under normal operation, the INSR
is written as the first part of each serial communication. The
instruction that is sent determines what type of communication
will occur next. It is not possible to read the INSR.