Datasheet

ADS1146
ADS1147
ADS1148
www.ti.com SBAS453F –JULY 2009–REVISED APRIL 2012
THERMAL INFORMATION
ADS1146,
ADS1147,
ADS1148
THERMAL METRIC
(1)
UNITS
PW
28
θ
JA
Junction-to-ambient thermal resistance
(2)
79.5
θ
JC(top)
Junction-to-case(top) thermal resistance
(3)
31.8
θ
JB
Junction-to-board thermal resistance
(4)
40.9
°C/W
ψ
JT
Junction-to-top characterization parameter
(5)
3.0
ψ
JB
Junction-to-board characterization parameter
(6)
41.1
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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