Datasheet

ADC122S625
SNAS451A –FEBRUARY 2008–REVISED MARCH 2013 www.ti.com
FUNCTIONAL DESCRIPTION
The ADC122S625 is a dual 12-bit, simultaneous sampling Analog-to-Digital (A/D) converter. The converter is
based on a successive-approximation register (SAR) architecture where the differential nature of the analog
inputs is maintained from the internal track-and-hold circuits throughout the A/D converter. The analog inputs on
both channels are sampled simultaneously to preserve their relative phase information to each other. The
architecture and process allow the ADC122S625 to acquire and convert dual analog signals at sample rates up
to 200 kSPS while consuming very little power.
The ADC122S625 requires an external reference, external clock, and an analog power supply. The analog
supply (V
A
) can range from 4.5V to 5.5V and the external reference can be any voltage between 1V and V
A
. The
value of the reference voltage determines the range of the analog input, while the reference input current
depends upon the conversion rate.
Analog inputs are presented at the inputs of Channel A and Channel B. Upon initiation of a conversion, the
differential input at these pins is sampled on the internal capacitor array. The analog input signals are
disconnected from the external circuitry while a conversion is in progress.
The external clock can take on values as indicated in the Electrical Characteristics Table. The duty cycle of the
clock is essentially unimportant, provided the minimum clock high and low times are met. The minimum clock
frequency is set by internal capacitor leakage. Each conversion requires thirty-two clock cycles to complete.
The ADC122S625 offers a high-speed serial data output that is binary 2's complement and compatible with
several standards, such as SPI™, QSPI™, MICROWIRE™, and many common DSP serial interfaces. The digital
conversion result of Channel A and Channel B is clocked out on the falling edges of the SCLK input and is
provided serially at D
OUT
, most significant bit first. The result of Channel A is output before the result of Channel
B, with four zeros in between the two results. The digital data provided on D
OUT
is that of the conversion currently
in progress. With CS held low after the result of Channel B is output, the ADC122S625 will continuously convert
the analog inputs until CS is de-asserted (brought high). Having a single, serial D
OUT
makes the ADC122S625 an
excellent replacement for two independent ADCs that are part of a daisy chain configuration and allows a system
designer to save valuable board space and power.
REFERENCE INPUT
The externally supplied reference voltage sets the analog input range. The ADC122S625 will operate with a
reference voltage in the range of 1V to V
A
.
Operation with a reference voltage below 1V is also possible with slightly diminished performance. As the
reference voltage (V
REF
) is reduced, the range of acceptable analog input voltages is reduced. Assuming a
proper common-mode input voltage, the differential peak-to-peak input range is limited to twice V
REF
. See Input
Common Mode Voltage for more details. Reducing the value of V
REF
also reduces the size of the least significant
bit (LSB). The size of one LSB is equal to twice the reference voltage divided by 4096. When the LSB size goes
below the noise floor of the ADC122S625, the noise will span an increasing number of codes and overall
performance will suffer. For example, dynamic signals will have their SNR degrade, while D.C. measurements
will have their code uncertainty increase. Since the noise is Gaussian in nature, the effects of this noise can be
reduced by averaging the results of a number of consecutive conversions.
Additionally, since offset and gain errors are specified in LSB, any offset and/or gain errors inherent in the A/D
converter will increase in terms of LSB size as the reference voltage is reduced.
The reference input and the analog inputs are connected to the capacitor array through a switch matrix when the
input is sampled. Hence, the current requirements at the reference and at the analog inputs are a series of
transient spikes that occur at a frequency dependent on the operating sample rate of the ADC122S625.
The reference current changes only slightly with temperature. See the curves, Reference Current vs. SCLK
Frequency and Reference Current vs. Temperature in the Typical Performance Characteristics section for
additional details.
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