Datasheet

I
OL
200 PA
I
OH
200 PA
1.6V
To Output Pin
C
L
35 pF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8
Track Hold
Power Up
Track Hold
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
9 10
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB11 DB10 DB9 DB8 DB7
DIN
DOUT
Power Up
SCLK
CS
Power Down
Control register
Control register
ADC122S101
SNAS286D –MARCH 2005–REVISED MARCH 2013 www.ti.com
ADC122S101 Timing Specifications (continued)
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, f
SCLK
= 8 MHz to 16 MHz, f
SAMPLE
= 500 ksps to
1 Msps, C
L
= 35 pF, Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol Parameter Conditions Typical Limits
(1)
Units
0.3 x
t
CL
SCLK Low Pulse Width 0.5 x t
SCLK
ns (min)
t
SCLK
V
A
= +3.0V 1.8
Output Falling
V
A
= +5.0V 1.3
t
DIS
CS Rising Edge to DOUT High-Impedance 20 ns (max)
V
A
= +3.0V 1.0
Output Rising
V
A
= +5.0V 1.0
Timing Diagrams
Figure 3. ADC122S101 Operational Timing Diagram
Figure 4. Timing Test Circuit
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