Datasheet

SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
t
BUF
ADC121C021, ADC121C021Q, ADC121C027
www.ti.com SNAS415F –JANUARY 2008–REVISED MARCH 2013
A.C. and Timing Characteristics (continued)
The following specifications apply for V
A
= +2.7V to +5.5V. Boldface limits apply for T
MIN
≤ T
A
≤ T
MAX
and all other limits are
at T
A
= 25°C, unless otherwise specified.
Units
Symbol Parameter Conditions
(1)
Typical
(2)
Limits
(2)
(Limits)
Standard Mode 250 ns (max)
20+0.1C
b
ns (min)
Fast Mode
250 ns (max)
t
fDA
Fall time of SDA signal
10 ns (min)
High Speed Mode, C
b
= 100pF
80 ns (max)
20 ns (min)
High Speed Mode, C
b
= 400pF
160 ns (max)
Standard Mode 1000 ns (max)
20+0.1C
b
ns (min)
Fast Mode
300 ns (max)
t
rCL
Rise time of SCL signal
10 ns (min)
High Speed Mode, C
b
= 100pF
40 ns (max)
20 ns (min)
High Speed Mode, C
b
= 400pF
80 ns (max)
Standard Mode 1000 ns (max)
20+0.1C
b
ns (min)
Fast Mode
300 ns (max)
Rise time of SCL signal after a
t
rCL1
repeated start condition and after an
10 ns (min)
High Speed Mode, C
b
= 100pF
acknowledge bit.
80 ns (max)
20 ns (min)
High Speed Mode, C
b
= 400pF
160 ns (max)
Standard Mode 300 ns (max)
20+0.1C
b
ns (min)
Fast Mode
300 ns (max)
t
fCL
Fall time of a SCL signal
10 ns (min)
High Speed Mode, C
b
= 100pF
40 ns (max)
20 ns (min)
High Speed Mode, C
b
= 400pF
80 ns (max)
Capacitive load for each bus line (SCL
C
b
400 pF (max)
and SDA)
Fast Mode 50 ns (max)
t
SP
Pulse Width of spike suppressed
(4)
High Speed Mode 10 ns (max)
(4) Spike suppression filtering on SCL and SDA will suppress spikes that are less than the indicated width.
Timing Diagrams
Figure 4. Serial Timing Diagram
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