Datasheet

ADC12130, ADC12132, ADC12138
www.ti.com SNAS098G –MARCH 2000–REVISED MARCH 2013
Table 3. ADC12130 and ADC12132 Multiplexer Addressing
(1)
Analog Channel Addressed and Assignment
ADC Input Polarity Multiplexer Output Channel
MUX Address with A/DIN1 tied to MUXOUT1 and A/DIN2 tied
Assignment Assignment
Mode
to MUXOUT2
DI0 DI1 CH0 CH1 COM A/DIN1 A/DIN2 MUXOUT1 MUXOUT2
L L + − + − CH0 CH1
Differential
L H − + − + CH0 CH1
H L + − + − CH0 COM
Single-Ended
H H + − + − CH1 COM
(1) ADC12130 do not have A/DIN1, A/DIN2, MUXOUT1 and MUXOUT2 pins.
Table 4. Mode Programming
(1)
ADC12138 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7
DO Format
Mode Selected
ADC12130
(next Conversion
(Current)
and DI0 DI1 DI2 DI3 DI4 DI5
Cycle)
ADC12132
See Table 2 or Table 3 L L L L 12 Bit Conversion 12 or 13 Bit MSB First
See Table 2 or Table 3 L L L H 12 Bit Conversion 16 or 17 Bit MSB First
See Table 2 or Table 3 L H L L 12 Bit Conversion 12 or 13 Bit LSB First
See Table 2 or Table 3 L H L H 12 Bit Conversion 16 or 17 Bit LSB First
L L L L H L L L Auto Cal No Change
L L L L H L L H Auto Zero No Change
L L L L H L H L Power Up No Change
L L L L H L H H Power Down No Change
L L L L H H L L Read Status Register No Change
L L L L H H L H Data Out without Sign No Change
H L L L H H L H Data Out with Sign No Change
L L L L H H H L Acquisition Time—6 CCLK Cycles No Change
L H L L H H H L Acquisition Time—10 CCLK Cycles No Change
H L L L H H H L Acquisition Time—18 CCLK Cycles No Change
H H L L H H H L Acquisition Time—34 CCLK Cycles No Change
L L L L H H H H User Mode No Change
Test Mode
H X X X H H H H No Change
(CH1–CH7 become Active Outputs)
(1) The ADC powers up with no Auto Cal, no Auto Zero, 10 CCLK acquisition time, 12-bit + sign conversion, power up, 12- or 13-bit MSB
First, and user mode.
X = Don't Care
Table 5. Conversion/Read Data Only Mode Programming
(1)
CS CONV PD Mode
L L L See Table 4 for Mode
L H L Read Only (Previous DO Format). No Conversion.
H X L Idle
X X H Power Down
(1) X = Don't Care
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