Datasheet

ADC12130, ADC12132, ADC12138
www.ti.com SNAS098G –MARCH 2000–REVISED MARCH 2013
Round off to the nearest integer value between −4096 to 4095 if the result of the above equation is not a whole
number.
Examples are shown in the table below:
V
REF
+
V
REF
−
V
IN
+
V
IN
−
Code Output Digital
+2.5V +1V +1.5V 0V 0,1111,1111,1111
+4.096V 0V +3V 0V 0,1011,1011,1000
+4.096V 0V +2.499V +2.500V 1,1111,1111,1111
+4.096V 0V 0V +4.096V 1,0000,0000,0000
5.0 INPUT CURRENT
At the start of the acquisition window (t
A
) a charging current flows into or out of the analog input pins (A/DIN1 and
A/DIN2) depending upon the input voltage polarity. The analog input pins are CH0–CH7 and COM when A/DIN1
is tied to MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value of this input current will depend upon the
actual input voltage applied, the source impedance and the internal multiplexer switch on resistance. With
MUXOUT1 tied to A/DIN1 and MUXOUT2 tied to A/DIN2 the internal multiplexer switch on resistance is typically
1.6 kΩ. The A/DIN1 and A/DIN2 mux on resistance is typically 750Ω.
6.0 INPUT SOURCE RESISTANCE
For low impedance voltage sources (<600Ω), the input charging current will decay, before the end of the S/H's
acquisition time of 2 μs (10 CCLK periods with f
CK
= 5 MHz), to a value that will not introduce any conversion
errors. For high source impedances, the S/H's acquisition time can be increased to 18 or 34 CCLK periods. For
less ADC accuracy and/or slower CCLK frequencies the S/H's acquisition time may be decreased to 6 CCLK
periods. To determine the number of clock periods (N
c
) required for the acquisition time with a specific source
impedance for the various resolutions the following equations can be used:
12 Bit + Sign N
C
= [R
S
+ 2.3] × f
CK
× 0.824
Where f
CK
is the conversion clock (CCLK) frequency in MHz and R
S
is the external source resistance in kΩ. As
an example, operating with a resolution of 12 Bits + sign, a 5 MHz clock frequency and maximum acquisition
time of 34 conversion clock periods the ADC's analog inputs can handle a source impedance as high as 6 kΩ.
The acquisition time may also be extended to compensate for the settling or response time of external circuitry
connected between the MUXOUT and A/DIN pins.
An acquisition starts at a falling edge of SCLK and ends at a rising edge of CCLK (see timing diagrams). If SCLK
and CCLK are asynchronous, one extra CCLK clock period may be inserted into the programmed acquisition
time for synchronization. Therefore, with asynchronous SCLK and CCLK, the acquisition time will change from
conversion to conversion.
7.0 INPUT BYPASS CAPACITANCE
External capacitors (0.01 μF–0.1 μF) can be connected between the analog input pins, CH0–CH7, and analog
ground to filter any noise caused by inductive pickup associated with long input leads. These capacitors will not
degrade the conversion accuracy.
8.0 NOISE
The leads to each of the analog multiplexer input pins should be kept as short as possible. This will minimize
input noise and clock frequency coupling that can cause conversion errors. Input filtering can be used to reduce
the effects of the noise sources.
9.0 POWER SUPPLIES
Noise spikes on the V
A
+
and V
D
+
supply lines can cause conversion errors; the comparator will respond to the
noise. The ADC is especially sensitive to any power supply spikes that occur during the Auto Zero or linearity
correction. The minimum power supply bypassing capacitors recommended are low inductance tantalum
capacitors of 10 μF or greater paralleled with 0.1 μF monolithic ceramic capacitors. More or different bypassing
may be necessary depending upon the overall system requirements. Separate bypass capacitors should be used
for the V
A
+
and V
D
+
supplies and placed as close as possible to these pins.
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