Datasheet

ADC12048
SNAS105B –APRIL 2000–REVISED MARCH 2013 www.ti.com
AUTO-ZERO CYCLE
During an auto-zero cycle, the offset is measured only once and a correction coefficient is created and stored in
an internal offset register. An auto-zero cycle is initiated by writing an Auto-Zero command to the ADC12048.
DIGITAL INTERFACE
The digital control signals are CS, RD, WR, RDY and STDBY. Specific timing relationships are associated with
the interaction of these signals. Refer to Digital Timing Diagrams for detailed timing specifications. The active low
RDY signal indicates when a certain event begins and ends. It is recommended that the ADC12048 should only
be accessed when the RDY signal is low. It is in this state that the ADC12048 is ready to accept a new
command. This will minimize the effect of noise generated by a switching data bus on the ADC. The only
exception to this is when the ADC12048 is in the standby mode at which time the RDY is high and the STDBY
signal is low. The ADC12048 is in the standby mode at power up or when a STANDBY command is issued. A
Ful-Cal, Auto-Zero, Reset or Start command will get the ADC12048 out of the standby mode. This may be
observed by monitoring the status of the RDY and STDBY signals. The RDY signal will go low and the STDBY
signal high when the ADC12048 leaves the standby mode.
The following describes the state of the digital control signals for each programmed event in both 8-bit and 13-bit
mode. RDY should be low before each command is issued except for the case when the device is in standby
mode.
FUL-CAL OR AUTO-ZERO COMMAND
8-bit mode: The first write to the ADC12048 will place the data in the lower byte of the Configuration register.
This byte must set the HB bit (b
7
) to allow access to the upper byte of the Configuration register during the next
write cycle. During the second write cycle, the Ful-Cal or Auto-Zero command must be issued. The edge of the
second write pulse on the WR pin will force the RDY signal high. At this time the converter begins executing a
full calibration or auto-zero cycle. The RDY signal will automatically go low when the full calibration or auto-zero
cycle is done.
13-bit mode: In a single write cycle the Ful-Cal or Auto-Zero command must be written to the ADC12048. The
edge of the WR signal will force the RDY high. At this time the converter begins executing a full calibration or
auto-zero cycle. The RDY signal will automatically go low when the full calibration or auto-zero cycle is done.
STARTING A CONVERSION: START COMMAND
In order to completely describe the events associated with the Start command, both the SYNC-OUT and SYNC-
IN modes must be considered.
SYNC-OUT/Asynchronous
8-bit mode: The first byte written to the ADC12048 should set the MUX channel, the acquisition time and the HB
bit. The second byte should clear the SYNC bit, write the START command and clear the BW bit. In order to
initiate a conversion, two reads must be performed from the ADC12048. The rising edge of the second read
pulse will force the RDY pin high and begin the programmed acquisition time selected by bits b
5
and b
4
of the
configuration register. The SYNC pin will go high indicating that a conversion sequence has begun following the
end of the acquisition period. The RDY and SYNC signal will fall low when the conversion is done. At this time
new information, such as a new MUX channel, acquisition time and operational command can be written into the
configuration register or it can remain unchanged. Assuming that the START command is in the Configuration
register, the previous conversion can be read. The first read places the lower byte of the conversion result
contained in the Data register on the data bus. The second read will place the upper byte of the conversion result
stored in the Data register on the data bus. The rising edge on the second read pulse will begin another
conversion sequence and raise the RDY and SYNC signals appropriately.
13-bit mode: The MUX channel and the acquisition time should be set, the SYNC bit cleared and the START
command issued with a single write to the ADC12048. In order to initiate a conversion, a single read must be
performed from the ADC12048. The rising edge of the read signal will force the RDY signal high and begin the
programmed acquisition time selected by bits b
5
and b
4
of the configuration register. The SYNC pin will go high
indicating that a conversion sequence has begun following the end of the acquisition period. The RDY and SYNC
signal will fall low when the conversion is done. At this time new information, such as a new MUX channel,
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