Datasheet

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ADC08200

www.ti.com

SNAS136M –APRIL 2001–REVISED MARCH 2013

ADC08200 8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sample-

and-Hold

Check for Samples: ADC08200

FEATURES

DESCRIPTION

The ADC08200 is a low-power, 8-bit, monolithic

• Single-Ended Input

analog-to-digital converter with an on-chip track-and-

• Internal Sample-and-Hold Function

hold circuit. Optimized for low cost, low power, small

• Low Voltage (Single +3V) Operation

size and ease of use, this product operates at

conversion rates up to 230 Msps while consuming

• Small Package

just 1.05 mW per MHz of clock frequency, or 210 mW

• Power-Down Feature

at 200 Msps. Raising the PD pin puts the ADC08200

into a Power Down mode where it consumes about 1

KEY SPECIFICATIONS

mW.

• Resolution 8 Bits

The unique architecture achieves 7.3 Effective Bits

• Maximum sampling frequency 200 Msps (min)

with 50 MHz input frequency. The ADC08200 is

resistant to latch-up and the outputs are short-circuit

• DNL ±0.4 LSB (typ)

proof. The top and bottom of the ADC08200's

• ENOB (f

= 50 MHz) 7.3 bits (typ)

reference ladder are available for connections,

• THD (f

= 50 MHz) 61 dB (typ)

enabling a wide range of input possibilities. The

digital outputs are TTL/CMOS compatible with a

• Power Consumption

separate output power supply pin to support

– Operating 1.05 mW/Msps (typ)

interfacing with 3V or 2.5V logic. The digital inputs

– Power Down 1 mW (typ)

(CLK and PD) are TTL/CMOS compatible. The output

data format is straight binary.

APPLICATIONS

The ADC08200 is offered in a 24-lead TSSOP

• Flat Panel Displays

package and, while specified over the industrial

temperature range of −40°C to +85°C, it will function

• Projection Systems

over the to −40°C to +105°C temperature range.

• Set-Top Boxes

• Battery-Powered Instruments

• Communications

• Medical Imaging

• Astronomy

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 ADC08200 8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sampleand-Hold Check for Samples: ADC08200 FEATURES DESCRIPTION • • • • • The ADC08200 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-andhold circuit. Optimized for low cost, low power, small size and ease of use, this product operates at conversion rates up to 230 Msps while consuming just 1.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com Block Diagram DR VD (pin 18) VA VRT 17 COARSE/FINE COMPARATORS 1 ENCODER & ERROR CORRECTION 8 17 8 MUX SWITCHES VRM 17 256 VRB ENCODER & ERROR CORRECTION 8 COARSE/FINE COMPARATORS VIN GND AGND PD 8 OUTPUT DRIVERS DATA OUT CLOCK GEN CLK VIN DR GND (pin 17) Pin Configuration Figure 1.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Equivalent Circuit Description 6 VIN Analog signal input. Conversion range is VRB to VRT. 3 VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 0.5V to VA. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See THE ANALOG INPUT for more information. 9 VRM Mid-point of the reference ladder.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Supply Voltage (VA) 3.8V Driver Supply Voltage (VDR) VA +0.3V Voltage on Any Input or Output Pin −0.3V to VA Reference Voltage (VRT, VRB) VA to AGND CLK, PD Voltage Range −0.05V to (VA + 0.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 Converter Electrical Characteristics The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1) (2) (3) Symbol Parameter Conditions Typical (4) Limits (4) Units (Limits) DC ACCURACY INL Integral Non-Linearity +1.0 −0.3 +1.9 −1.2 LSB (max) LSB (min) DNL Differential Non-Linearity ±0.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com Converter Electrical Characteristics (continued) The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C (1)(2)(3) Symbol Parameter Conditions Typical (4) Limits (4) Units (Limits) DIGITAL OUTPUT CHARACTERISTICS VOH High Level Output Voltage VA = VDR = 2.7V, IOH = −400 µA 2.6 2.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 Converter Electrical Characteristics (continued) The following specifications apply for VA = VDR = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 5 pF, fCLK = 200 MHz at 50% duty cycle.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the rise of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after the clock goes high. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as input noise.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated 10 INL INL vs. Temperature Figure 3. Figure 4. INL vs. Supply Voltage INL vs. Sample Rate Figure 5. Figure 6. DNL DNL vs. Temperature Figure 7. Figure 8.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated DNL vs. Supply Voltage DNL vs. Sample Rate Figure 9. Figure 10. SNR vs. Temperature SNR vs. Supply Voltage Figure 11. Figure 12. SNR vs. Sample Rate SNR vs. Input Frequency Figure 13. Figure 14.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated 12 SNR vs. Clock Duty Cycle Distortion vs. Temperature Figure 15. Figure 16. Distortion vs. Supply Voltage Distortion vs. Sample Rate Figure 17. Figure 18. Distortion vs. Input Frequency Distortion vs. Clock Duty Cycle Figure 19. Figure 20.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated SINAD/ENOB vs. Temperature SINAD/ENOB vs. Supply Voltage Figure 21. Figure 22. SINAD/ENOB vs. Sample Rate SINAD/ENOB vs. Input Frequency Figure 23. Figure 24. SINAD/ENOB vs. Clock Duty Cycle Power Consumption vs. Sample Rate Figure 25. Figure 26.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = VDR = 3V, fCLK = 200 MHz, fIN = 50 MHz, unless otherwise stated 14 Spectral Response @ fIN = 50 MHz Spectral Response @ fIN = 76 MHz Figure 27. Figure 28. Spectral Response @ fIN = 99 MHz Intermodulation Distortion Figure 29. Figure 30.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The ADC08200 uses a new, unique architecture that achieves over 7 effective bits at input frequencies up to and beyond 100 MHz. The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRT will cause the output word to consist of all ones.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com The reference bias circuit of Figure 31 is very simple and the performance is adequate for many applications. However, circuit tolerances will lead to a wide reference voltage range. Better reference stability can be achieved by driving the reference pins with low impedance sources. The circuit of Figure 32 will allow a more accurate setting of the reference voltages.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 Figure 33 shows an example of an input circuit using the LMH6702. Any input amplifier should incorporate some gain as operational amplifiers exhibit better phase margin and transient response with gains above 2 or 3 than with unity gain. If an overall gain of less than 3 is required, attenuate the input and operate the amplifier at a higher gain, as shown in Figure 33.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com While a single voltage source is recommended for the VA and VDR supplies of the ADC08200, these supply pins should be well isolated from each other to prevent any digital noise from being coupled into the analog portions of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass capacitors close to the supply pins.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 This termination should be located as close as possible to, but within one centimeter of, the ADC08200 clock pin. Further, this termination should be close to but beyond the ADC08200 clock pin as seen from the clock source. Typical tprop is about 150 ps/inch on FR-4 board material.
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ADC08200 SNAS136M – APRIL 2001 – REVISED MARCH 2013 www.ti.com Figure 34 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed together away from any digital components. DYNAMIC PERFORMANCE The ADC08200 is a.c. tested and its dynamic performance is ensured. To meet the published specifications, the clock source driving the CLK input must exhibit less than 2 ps (rms) of jitter. For best a.c.
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ADC08200 www.ti.com SNAS136M – APRIL 2001 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision L (March 2013) to Revision M • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC08200CIMTX/NOPB Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC08200CIMTX/NOPB TSSOP PW 24 2500 367.0 367.0 35.
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