Datasheet
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
182/255 DocID029041 Rev 6
JTAG/SWD timing diagrams
Figure 52. JTAG timing diagram
Table 89. Dynamics characteristics: SWD characteristics
Symbol Parameter Conditions Min Typ Max Unit
F
pp
SWCLK clock frequency
2.7V <VDD< 3.6V - - 80
MHz
1/t
c(SWCLK)
1.71 <VDD< 3.6V
--50
t
w(SWCLKH)
SCK high and low time - T
PCLK
1T
PCLK
T
PCLK
+ 1
ns
t
w(SWCLKL)
t
su(SWDIO)
SWDIO input setup time - 3.5 - -
t
h(SWDIO)
SWDIO input hold time - 0 - -
t
ov (SWDIO)
SWDIO output valid time
2.7V <VDD< 3.6V - 11 12
1.71 <VDD< 3.6V
- 11 16.5
t
oh(SWDIO)
SWDIO output hold time - 9 - -
06Y9
7',706
7&.
7'2
W
F7&.
W
Z7&./
W
Z7&.+
W
K7067',
W
VX7067',
W
RY7'2
W
RK7'2
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