Datasheet

DocID029041 Rev 6 177/255
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics
220
Figure 47. SPI timing diagram - slave mode and CPHA = 0
tsu(MI)
Data input setup time
Master mode
4
9
(4)
--
ns
tsu(SI) Slave mode 4.5 - -
th(MI)
Data input hold time
Master mode
3
0
(4)
--
th(SI) Slave mode 2 - -
ta(SO) Data output access time Slave mode 7 - 21
tdis(SO) Data output disable time Slave mode 5 - 12
tv(SO)
Data output valid time
Slave mode 2.7VDD3.6V - 6.5 10
Slave mode 1.71VDD3.6V - 6.5 13.5
tv(MO) Master mode - 2 6
th(SO)
Data output hold time
Slave mode
1.71VDD3.6V
4.5 - -
th(MO) Master mode 0 - -
1. Guaranteed by characterization results.
2. Excepting SPI1 with SCK IO pin mapped on PA5. In this configuration, Maximum achievable frequency is 40MHz.
3. Maximum Frequency of Slave Transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK
level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having
Tsu(MI)=0 while signal Duty(SCK)=50%.
4. Only for SPI6.
Table 86. SPI dynamic characteristics
(1)
(continued)
Symbol Parameter Conditions Min Typ Max Unit
06Y9
166LQSXW
&3+$ 
&32/ 
6&.LQSXW
&3+$ 
&32/ 
0,62RXWSXW
026,LQSXW
W
VX6,
W
K6,
W
Z6&./
W
Z6&.+
W
F6&.
W
U6&.
W
K166
W
GLV62
W
VX166
W
D62
W
Y62
1H[WELWV,1
/DVWELW287
)LUVWELW,1
)LUVWELW287 1H[WELWV287
W
K62
W
I6&.
/DVWELW,1
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