Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 2MB TFBGA

This is information on a product in full production.

September 2017 DocID029041 Rev 6 1/255

STM32F765xx STM32F767xx

STM32F768Ax STM32F769xx

Arm

Cortex

-M7 32b MCU+FPU, 462DMIPS, up to 2MB Flash/

512+16+4KB RAM, USB OTG HS/FS, 28 com IF, LCD, DSI

Datasheet - production data

Features

• Core: Arm

32-bit Cortex

-M7 CPU with

DPFPU

, ART Accelerator

™

and L1-cache:

16 Kb

ytes I/D cache, allowing 0-wait stat

executio

n from embedded Flash and exter

nal

mories, up to 216 MHz, MP

2 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1)

d DSP instructions.

• Memories

– Up to 2 Mbytes of Flash memory organized

into two banks allowing read-while-write

– SRAM: 512 Kbytes (including 128 Kbyt

of dat

a TCM RAM for critical real-time data)

+ 16 Kbytes of instruction TCM

RAM (for

ritical real-time routines) + 4 Kbytes of

backup SRAM

– Flexible external memory controller with up

to 32-bit dat

a bus: SRAM, PSRAM,

RAM/LPSDR SDRAM, NOR/NA

mem

ories

• Dual mode Quad-SPI

• Graphics

– Chrom-ART Accelerator

™

(DMA2D),

graphical hardware accelerator enablin

enh

anced graphical user interface

– Hardware JPEG codec

– LCD-TFT controller supporting up to

XGA

solution

–MIPI

DSI host controller supporting up to

720p 30 Hz resolution

• Clock, reset and supply management

– 1.7 V to 3.6 V application supply and I/Os

– POR, PDR, PVD and BOR

– Dedicated USB power

– 4-to-26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC (1

curacy)

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Low-power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 32×32 bit backup

regist

ers + 4 Kbytes backup SRAM

• 3×12-bit, 2.4 MSPS ADC: up to 24 channels

• Digital filters for sigma delta modulator

(DFSDM), 8 channels / 4 filters

• 2×12-bit D/A converters

• General-purpose DMA: 16-strea

m DMA

contr

oller with FIFOs and burst support

• Up to 18 timers: up to thirteen 16-bit (1x low-

power 16-bit timer available in Stop mode) and

two 32-bit timers, each with

up to 4

IC/OC/PWM or pu

lse counter and quadratur

(

incremental) encoder input. All 15 timers

running up to 216 MHz. 2x watchd

ogs, SysTick

timer

• Deb

ug mode

– SWD & JTAG interfaces

–Cortex

-M7 Trace Macrocell

™

• Up to 168 I/O ports with interrupt capability

– Up to 164 fast I/Os up to 108 MHz

– Up to 166 5 V-tolerant I/Os

LQFP100 (14 × 14 mm)

UFBGA176 (10 x 10 mm)

&"'!

TFBGA216 (13 x 13 mm)

LQFP208 (28 x 28 mm)

WLCSP180

(0.4 mm pitch)

LQFP176 (24 × 24 mm)

LQFP144 (20 × 20 mm)

TFBGA100 (8 x 8 mm)

www.st.com

Downloaded from Arrow.com.

Summary of content (255 pages)

PAGE 1
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Arm® Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 2MB Flash/ 512+16+4KB RAM, USB OTG HS/FS, 28 com IF, LCD, DSI Datasheet - production data Features • Core: Arm® 32-bit Cortex®-M7 CPU with DPFPU, ART Accelerator™ and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded Flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions.
PAGE 2
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx • Up to 28 communication interfaces – Up to 4 I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/4 UARTs (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) – Up to 6 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2S for audio – 2 x SAIs (serial audio interface) – 3 × CANs (2.0B Active) and 2x SDMMCs – SPDIFRX interface – HDMI-CEC – MDIO slave interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.
PAGE 3
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 Arm® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.
PAGE 4
Contents STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.23.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.23.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.23.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.23.6 Window watchdog . . . . .
PAGE 5
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5 Contents Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.3 Typical curves . . . .
PAGE 6
Contents 6 7 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 5.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 5.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 5.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 5.3.
PAGE 7
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 8
List of tables Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. 8/255 Downloaded from Arrow.com.
PAGE 9
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of tables Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119.
PAGE 10
List of tables STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 129. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Table 130. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Table 131.
PAGE 11
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40.
PAGE 12
List of figures Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90.
PAGE 13
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. List of figures LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . .
PAGE 14
Description 1 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a floating point unit (FPU) which supports Arm® double-precision and single-precision data-processing instructions and data types.
PAGE 15
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description These features make the STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx microcontrollers suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances • Mobile applications, Internet of Things • Wearable devices: smartwatches The followin
PAGE 16
/255 Downloaded from Arrow.com.
PAGE 17
Downloaded from Arrow.com. 129 STM32F 768Ax Yes 140 No STM32F 765Ix DocID029041 Rev 6 LQFP208 159 Yes STM32F767 /769Bx 7. UFBGA176 is not available for STM32F769x sales types. 6. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.18.2: Internal reset OFF). 159 Yes STM32F767 /769Nx TFBGA216 168 No STM32F 765Nx 5.
PAGE 18
Description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Full compatibility throughout the family The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are fully pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1 gives compatible board designs between the STM32F7xx and STM32F4xx families. Figure 1.
PAGE 19
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Description Figure 2. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx block diagram 86% '0$ 27* +6 ),)2 *3 '0$ 6WUHDPV ),)2 *3 '0$ 6WUHDPV ),)2 /&' 7)7 ),)2 *3,2 3257 % 3&> @ *3,2 3257 & 3'> @ *3,2 3257 ' 3(> @ *3,2 3257 ( 3)> @ *3,2 3257 ) 3*> @ *3,2 3257 * 3+> @ *3,2 3257 + ),)2 #9'' 9'' %%JHQ 32:(5 01*7 92/7 5(* 9 72 9 /6 (;7 ,7 :.
PAGE 20
Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2 Functional overview 2.1 Arm® Cortex®-M7 with FPU The Arm® Cortex®-M7 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering an outstanding computational performance and low interrupt latency.
PAGE 21
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.3 Functional overview Embedded Flash memory The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices embed a Flash memory of up to 2 Mbytes available for storing programs and data. The Flash interface features: 2.4 • Single /or Dual bank operating modes, • Read-While-Write (RWW) in Dual bank mode.
PAGE 22
Functional overview 2.
PAGE 23
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.7 Functional overview DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB).
PAGE 24
Functional overview 2.
PAGE 25
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.10 Functional overview LCD-TFT controller The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to XGA (1024x768) resolution with the following features: 2.
PAGE 26
Functional overview 2.13 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx JPEG codec (JPEG) The JPEG codec provides an fast and simple hardware compressor and decompressor of JPEG images with full management of JPEG headers. The JPEG codec main features: 2.
PAGE 27
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio class performance. In this case, the I2S and SAI master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.
PAGE 28
Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx disappear.
PAGE 29
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 5. VDDUSB connected to external power supply 9''86%B0$; 86% IXQFWLRQDO DUHD 9''86% 9''86%B0,1 86% QRQ IXQFWLRQDO DUHD 9'' 9''$ 86% QRQ IXQFWLRQDO DUHD 9''B0,1 2SHUDWLQJ PRGH 3RZHU RQ WLPH 3RZHU GRZQ 06 9 The DSI (Display Serial Interface) sub-system uses several power supply pins which are independent from the other supply pins: • VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI D-PHY.
PAGE 30
Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold.
PAGE 31
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 7. PDR_ON control with internal reset OFF 9 '' 3'5 9 WLPH 5HVHW E\ RWKHU VRXUFH WKDQ SRZHU VXSSO\ VXSHUYLVRU 1567 3'5B21 3'5B21 WLPH 06 9 2.19 Voltage regulator The regulator has four operating modes: • • 2.19.
PAGE 32
Functional overview • STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: • – LPR operates in normal mode (default mode when LPR is ON) – LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode.
PAGE 33
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Figure 8. Regulator OFF 9 ([WHUQDO 9&$3B SRZHU $SSOLFDWLRQ UHVHW VXSSO\ VXSHUYLVRU ([W UHVHW FRQWUROOHU DFWLYH VLJQDO RSWLRQDO ZKHQ 9&$3B 0LQ 9 9'' 3$ 9'' 1567 %<3$66B5(* 9 9&$3B 9&$3B DL 9 The following conditions must be respected: Note: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.
PAGE 34
Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 9. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1,VCAP_2 stabilization 9'' 3'5 RU 9 9 0LQ 9 9&$3B 9&$3B WLPH 1567 3$ WLPH DL J 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 10.
PAGE 35
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.19.3 Functional overview Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package Regulator ON Regulator OFF LQFP100 LQFP144, LQFP208 LQFP176, UFBGA176, TFBGA100, TFBGA216 WLCSP180 Yes Internal reset ON Internal reset OFF Yes No No Yes Yes Yes Yes BYPASS_REG set BYPASS_REG set PDR_ON set to VDD PDR_ON set to VSS to VDD to VSS Yes(1) 1.
PAGE 36
Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx The RTC clock sources can be: • A 32.768 kHz external crystal (LSE) • An external resonator or oscillator(LSE) • The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) • The high-speed external clock (HSE) divided by 32 The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE.
PAGE 37
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11), or an RTC alarm / wakeup / tamper /time stamp event occurs.
PAGE 38
Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 6.
PAGE 39
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.23.1 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers.
PAGE 40
Functional overview 2.23.4 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Low-power timer (LPTIM1) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 2.23.
PAGE 41
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.24 Functional overview Inter-integrated circuit interface (I2C) The devices embed 4 I2C. Refer to table Table 7: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: • • I2C-bus specification and user manual rev.
PAGE 42
Functional overview 2.25 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Universal synchronous/asynchronous receiver transmitters (USART) The devices embed USART. Refer to Table 8: USART implementation for the features implementation. The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format.
PAGE 43
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Functional overview Table 8. USART implementation (continued) features(1) USART1/2/3/6 UART4/5/7/8 Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X 1. X: supported. 2.
PAGE 44
Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SAI1 and SAI2 can be served by the DMA controller 2.28 SPDIFRX Receiver Interface (SPDIFRX) The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC-61937. These standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up to 5.1).
PAGE 45
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.31 Functional overview SD/SDIO/MMC card host interface (SDMMC) SDMMC host interfaces are available, that support the MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDMMC Card Specification Version 2.
PAGE 46
Functional overview 2.33 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Controller area network (bxCAN) The three CANs are compliant with the 2.0A and B (active) specifications with a bit rate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used).
PAGE 47
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.36 Functional overview • Software configurable to OTG1.3 and OTG2.0 modes of operation • USB 2.0 LPM (Link Power Management) support • Battery Charging Specification Revision 1.2 support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output.
PAGE 48
Functional overview 2.38 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Management Data Input/Output (MDIO) slaves The devices embed a MDIO slave interface it includes the following features: • – 32 x 16-bit firmware read/write, MDIO read-only output data registers – 32 x 16-bit firmware read-only, MDIO write-only input data registers • Configurable slave (port) address • Independently maskable interrupts/events: • 2.
PAGE 49
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.42 Functional overview Digital filter for Sigma-Delta Modulators (DFSDM) The devices embed one DFSDM with 4 digital filters modules and 8 external input serial channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to perform digital filtering of the received data streams (which represent analog value on Σ∆ modulators inputs).
PAGE 50
Functional overview – STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Refreshed by software • DMA capability to read the final conversion data • Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial channel clock absence • “regular” or “injected” conversions: – “regular” conversions can be requested at any time or even in continuous mode without having any impact on the timing of “injected” conversions – “injected” conversions for precise timing and with high convers
PAGE 51
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 2.43 Functional overview Temperature sensor The temperature sensor has to generate a voltage that varies linearly with the temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value.
PAGE 52
Functional overview STM32F765xx STM32F767xx STM32F768Ax STM32F769xx any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. 2.
PAGE 53
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx – Video mode – Adapted Command mode – APB Slave Functional overview Video Mode interfaces features: • LTDC interface color coding mappings into 24-bit interface: – 16-bit RGB, configurations 1, 2, and 3 – 18-bit RGB, configurations 1 and 2 – 24-bit RGB • Programmable polarity of all LTDC interface signals • Maximum resolution is limited by available DSI physical link bandwidth: – Number of lanes: 2 – Maximum speed per lane: 500 Mbps1Gbps A
PAGE 54
Pinouts and pin description 3 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description ϭϬϬ ϵϵ ϵϴ ϵϳ ϵϲ ϵϱ ϵϰ ϵϯ ϵϮ ϵϭ ϵϬ ϴϵ ϴϴ ϴϳ ϴϲ ϴϱ ϴϰ ϴϯ ϴϮ ϴϭ ϴϬ ϳϵ ϳϴ ϳϳ ϳϲ s s^^ W ϭ W Ϭ W ϵ W ϴ KKdϬ W ϳ W ϲ W ϱ W ϰ W ϯ W ϳ W ϲ W ϱ W ϰ W ϯ W Ϯ W ϭ W Ϭ W ϭϮ W ϭϭ W ϭϬ W ϭϱ W ϭϰ Figure 11.
PAGE 55
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Figure 12.
PAGE 56
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6$$ 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 13.
PAGE 57
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 14.
PAGE 58
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$3$--# 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 15.
PAGE 59
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Figure 16. STM32F769Ax/STM32F768Ax WLCSP180 ballout $ 1& 1& 3$ -7&. 6:&/.
PAGE 60
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx ϭ Ϯ ϯ ϰ ϱ ϲ ϳ ϴ ϵ ϭϬ ϭϭ ϭϮ ϭϯ ϭϰ ϭϱ ϭϲ ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ Ϯϵ ϯϬ ϯϭ ϯϮ ϯϯ ϯϰ ϯϱ ϯϲ ϯϳ ϯϴ ϯϵ ϰϬ ϰϭ ϰϮ ϰϯ ϰϰ ϰϱ ϰϲ ϰϳ ϰϴ ϰϵ ϱϬ ϱϭ ϱϮ >Y&WϮϬϴ ϭϱϲ ϭϱϱ ϭϱϰ ϭϱϯ ϭϱϮ ϭϱϭ ϭϱϬ ϭϰϵ ϭϰϴ ϭϰϳ ϭϰϲ ϭϰϱ ϭϰϰ ϭϰϯ ϭϰϮ ϭϰϭ ϭϰϬ ϭϯϵ ϭϯϴ ϭϯϳ ϭϯϲ ϭϯϱ ϭϯϰ ϭϯϯ ϭϯϮ ϭϯϭ ϭϯϬ ϭϮϵ ϭϮϴ ϭϮϳ ϭϮϲ ϭϮϱ ϭϮϰ ϭϮϯ ϭϮϮ ϭϮϭ ϭϮϬ ϭϭϵ ϭϭϴ ϭϭϳ ϭϭϲ ϭϭϱ ϭϭϰ ϭϭϯ ϭϭϮ ϭϭϭ ϭϭϬ ϭϬϵ ϭϬϴ ϭϬϳ ϭϬϲ ϭϬϱ W/Ϯ W/ϭ W/Ϭ W,ϭϱ W,ϭϰ W,ϭϯ s s^^ s WͺϮ W ϭϯ W ϭϮ W ϭϭ W ϭϬ W ϵ W
PAGE 61
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description ϭ Ϯ ϯ ϰ ϱ ϲ ϳ ϴ ϵ ϭϬ ϭϭ ϭϮ ϭϯ ϭϰ ϭϱ ϭϲ ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ Ϯϵ ϯϬ ϯϭ ϯϮ ϯϯ ϯϰ ϯϱ ϯϲ ϯϳ ϯϴ ϯϵ ϰϬ ϰϭ ϰϮ ϰϯ ϰϰ ϰϱ ϰϲ ϰϳ ϰϴ ϰϵ ϱϬ ϱϭ ϱϮ /4)3 ZLWK '6, ϭϱϲ ϭϱϱ ϭϱϰ ϭϱϯ ϭϱϮ ϭϱϭ ϭϱϬ ϭϰϵ ϭϰϴ ϭϰϳ ϭϰϲ ϭϰϱ ϭϰϰ ϭϰϯ ϭϰϮ ϭϰϭ ϭϰϬ ϭϯϵ ϭϯϴ ϭϯϳ ϭϯϲ ϭϯϱ ϭϯϰ ϭϯϯ ϭϯϮ ϭϯϭ ϭϯϬ ϭϮϵ ϭϮϴ ϭϮϳ ϭϮϲ ϭϮϱ ϭϮϰ ϭϮϯ ϭϮϮ ϭϮϭ ϭϮϬ ϭϭϵ ϭϭϴ ϭϭϳ ϭϭϲ ϭϭϱ ϭϭϰ ϭϭϯ ϭϭϮ ϭϭϭ ϭϭϬ ϭϬϵ ϭϬϴ ϭϬϳ ϭϬϲ ϭϬϱ W/Ϯ W/ϭ W/Ϭ W,ϭϱ W,ϭϰ W,ϭϯ s s^^ s WͺϮ W ϭϯ W ϭϮ W ϭϭ W
PAGE 62
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 19.
PAGE 63
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Figure 20. STM32F76xxx TFBGA216 ballout ! 0% 0% 0% 0' 0% 0% 0" 0" 0" 0" 0$ " 0% 0% 0' 0" 0" 0" 0' 0' 0* 0* # 6"!4 0) 0) 0+ 0+ 0+ 0' 0' 0* $ 0# 0& 0) 0) 0) 0) 0+ 0+ 0' % 0# 0& 0) 0) 0$2? /.
PAGE 64
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 21. STM32F769xx TFBGA216 ballout ! 0% 0% 0% 0' 0% 0% 0" 0" 0" 0" 0$ " 0% 0% 0' 0" 0" 0" 0' 0' 0* 0* # 6"!4 0) 0) 0+ 0+ 0+ 0' 0' 0* $ 0# 0& 0) 0) 0) 0) 0+ 0+ 0' % 0# 0& 0) 0) 0$2? /.
PAGE 65
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 10. Legend/abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TTa 3.
PAGE 66
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 67
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11.
PAGE 68
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 69
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11.
PAGE 70
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 71
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11.
PAGE 72
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 73
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11.
PAGE 74
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 75
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11.
PAGE 76
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 77
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11.
PAGE 78
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 79
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11.
PAGE 80
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 81
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11.
PAGE 82
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 83
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 11.
PAGE 84
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 11.
PAGE 85
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 12.
PAGE 86
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 12. FMC pin definition (continued) 86/255 Downloaded from Arrow.com.
PAGE 87
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Pinouts and pin description Table 12.
PAGE 88
/255 Downloaded from Arrow.com.
PAGE 89
Downloaded from Arrow.com.
PAGE 90
/255 Downloaded from Arrow.com.
PAGE 91
Downloaded from Arrow.com.
PAGE 92
/255 Downloaded from Arrow.com.
PAGE 93
Downloaded from Arrow.com.
PAGE 94
/255 Downloaded from Arrow.com.
PAGE 95
Downloaded from Arrow.com.
PAGE 96
/255 Downloaded from Arrow.com.
PAGE 97
Downloaded from Arrow.com.
PAGE 98
/255 Downloaded from Arrow.com.
PAGE 99
Downloaded from Arrow.com.
PAGE 100
/255 Downloaded from Arrow.com.
PAGE 101
Downloaded from Arrow.com.
PAGE 102
Memory mapping 4 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Memory mapping The memory map is shown in Figure 22. Figure 22. Memory map [)))) )))) 5HVHUYHG [( [)))) )))) &RUWH[ 0 LQWHUQDO SHULSKHUDOV [( [( ) )))) $+% [ ['))) )))) 5HVHUYHG [ & [ ))) )))) [ %)) $+% 0E\WH %ORFN &RUWH[ 0 ,QWHUQDO SHULSKHUDOV 5HVHUYHG [ [ [ ))) )))) [ )))) [( ['))) )))) 0E\WH %ORFN )0& ['
PAGE 103
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Memory mapping Table 14.
PAGE 104
Memory mapping STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 14.
PAGE 105
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Memory mapping Table 14.
PAGE 106
Memory mapping STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 14.
PAGE 107
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5 Electrical characteristics Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.
PAGE 108
Electrical characteristics 5.1.6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Power supply scheme Figure 25. STM32F769xx/STM32F779xx power supply scheme 9%$7 %DFNXS FLUFXLWU\ 26& . 57& :DNHXS ORJLF %DFNXS UHJLVWHUV EDFNXS 5$0 287 *3 , 2V ,1 /HYHO VKLIWHU 3RZHU VZLWFK 9%$7 WR 9 ,2 /RJLF 287 3*> @ 3'> @ ,1 î ) 9'' 9''86% ,2 /RJLF .
PAGE 109
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 26. STM32F767xx/STM32F777xx power supply scheme 9 %$7 9 ''6'00& 287 3*> @ 3'> @ ,1 287 3$> @ 3%> @ 9 ''86% ,1 9''86% /HYHO VKLIWHU ,1 9 ''6'00& /HYHO VKLIWHU *3 , 2 V /HYHO VKLIWHU 287 Q) ) EDFNXS FLUFXLWU\ 26& .
PAGE 110
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 5.1.
PAGE 111
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Applicable only for STM32F7x9 sales types. 2. All main power (VDD, VDDA, VDDSDMMC, VDDUSB, VDDDSI) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 3. VIN maximum value must always be respected. Refer to Table 16 for the values of the maximum allowed injected current. 4. Include VREF- pin. Table 16. Current characteristics Symbol Ratings Max.
PAGE 112
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3 Operating conditions 5.3.1 General operating conditions Table 18.
PAGE 113
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 18. General operating conditions (continued) Symbol Min Typ Max Power Scale 3 ((VOS[1:0] bits in PWR_CR register = 0x01), 144 MHz HCLK max frequency 1.08 1.14 1.20 Power Scale 2 ((VOS[1:0] bits in PWR_CR register = 0x10), 168 MHz HCLK max frequency with over-drive OFF or 180 MHz with over-drive ON 1.20 1.26 1.
PAGE 114
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 7. The over-drive mode is not supported when the internal regulator is OFF. 8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled 9.
PAGE 115
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 20. VCAP1/VCAP2 operating conditions(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 µF ESR ESR of external capacitor <2Ω 1. When bypassing the voltage regulator, the two 2.2 µF VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. 5.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA.
PAGE 116
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 23. Reset and power control block characteristics Symbol VPVD Parameter Conditions Programmable voltage detector level selection VPVDhyst(1) PVD hysteresis VPOR/PDR Power-on/power-down reset threshold Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V PLS[2:0]=001 (falling edge) 2.13 2.19 2.
PAGE 117
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Guaranteed by design. 2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first instruction is read by the user application code. 5.3.6 Over-drive switching characteristics When the over-drive mode switches from enabled to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up.
PAGE 118
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load). • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted both to fHCLK frequency and VDD range (see Table 19: Limitations depending on the operating power supply range).
PAGE 119
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 4. Guaranteed by test in production. Table 26.
PAGE 120
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 27.
PAGE 121
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 28.
PAGE 122
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 29.
PAGE 123
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 30.
PAGE 124
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 31.
PAGE 125
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 32.
PAGE 126
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. Table 34.
PAGE 127
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 35.
PAGE 128
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 37. Typical and maximum current consumptions in Standby mode Typ(1) Symbol Parameter Max(2) TA = 25 °C TA = 25 °C Conditions VDD = VDD= VDD = 1.7 V 2.4 V 3.3 V TA = 85 °C TA = 105 °C VDD = 3.3 V Backup SRAM OFF, RTC and LSE OFF 1.1 1.9 2.4 5(3) 18(3) 38(3) Backup SRAM ON, RTC and LSE OFF 1.9 2.7 3.2 6(3) 23(3) 48(3) Backup SRAM OFF, RTC ON and LSE in low drive mode 1.7 2.7 3.
PAGE 129
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 38. Typical and maximum current consumptions in VBAT mode Symbol Parameter Typ Max(2) TA =25 °C TA =85 °C TA =105 °C VBAT = VBAT= VBAT= 1.7 V 2.4 V 3.3 V VBAT = 3.6 V Conditions(1) Backup SRAM OFF, RTC and LSE OFF 0.03 0.04 0.04 0.2 0.4 Backup SRAM ON, RTC and LSE OFF 0.77 0.78 0.83 3.2 7.4 Backup SRAM OFF, RTC ON and LSE in low drive mode 0.62 0.8 1.13 4.4 10.
PAGE 130
Electrical characteristics Caution: STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode.
PAGE 131
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 39. Switching output I/O current consumption(1) (continued) I/O toggling Symbol Parameter Conditions frequency (fsw) MHz Typ Typ VDD = 3.3 V VDD = 1.8 V 2 0.3 0.1 8 1.0 0.5 25 3.5 1.6 50 5.9 4.2 60 10.0 4.4 84 19.12 5.8 90 19.6 - 2 0.3 0.2 8 1.3 0.7 25 3.5 2.3 50 10.26 5.19 60 16.
PAGE 132
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 40. Peripheral current consumption IDD(Typ)(1) Peripheral AHB1 (up to 216 MHz) AHB2 (up to 216 MHz) AHB3 (up to 216 MHz) Scale 2 Scale 3 GPIOA 2.9 2.8 2.2 GPIOB 3.0 2.9 2.2 GPIOC 2.9 2.8 2.2 GPIOD 3.1 3.0 2.3 GPIOE 3.1 3.0 2.3 GPIOF 2.9 2.8 2.2 GPIOG 2.9 2.8 2.2 GPIOH 3.1 3.1 2.4 GPIOI 3.0 2.9 2.2 GPIOJ 2.9 2.9 2.2 GPIOK 2.8 2.8 2.4 CRC 1.0 0.9 0.8 BKPSRAM 0.9 0.9 0.
PAGE 133
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 40. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral Scale 2 Scale 3 TIM2 19.1 18.7 14.7 TIM3 14.6 14.0 10.6 TIM4 15.4 14.7 11.4 TIM5 18.1 17.6 13.6 TIM6 3.1 2.7 1.4 TIM7 3.0 2.7 1.1 TIM12 8.1 7.8 5.6 TIM13 5.4 5.1 3.1 TIM14 5.6 5.3 3.3 LPTIM1 9.8 9.6 6.9 WWDG APB1 (up to 54 MHz) Unit Scale 1 1.9 1.6 1,4 (3) SPI2/I2S2 3.0 2.9 1.4 SPI3/I2S3(3) 3.0 3.
PAGE 134
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 40. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral Scale 2 Scale 3 TIM1 24.1 23.8 19.6 TIM8 24.5 24.2 20.0 USART1 17.7 17.4 14.3 USART6 11.9 11.8 9.4 ADC1(5) 4.5 4.7 3.5 ADC2 (5) 4.5 4.7 3.3 ADC3 (5) 4.5 4.6 3.3 SDMMC1 8.4 8.3 6.9 SDMMC2 8.2 8.2 6.4 3.9 3.6 3.1 SPI4 3.9 3.6 3.1 SYSCFG 2.5 2.2 1.9 TIM9 8.0 8.0 6.2 TIM10 5.0 5.1 3.7 TIM11 6.9 6.
PAGE 135
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.8 Electrical characteristics Wakeup time from low-power modes The wakeup times given in Table 41 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: • For Stop or Sleep modes: the wakeup event is WFE. • WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 41.
PAGE 136
Electrical characteristics 5.3.9 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 66: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 29.
PAGE 137
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 43. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD VSS - 0.
PAGE 138
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 30. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU /6( WI /6( W W: /6( W: /6( 7/6( I/6(BH[W ([WHUQDO FORFN VRXUFH ,/ 26& B,1 670 ) DL High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator.
PAGE 139
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 31). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
PAGE 140
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 45. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) (continued) Symbol Parameter Gm_crit_max Maximum critical crystal gm tSU(2) Conditions Min Typ Max LSEDRV[1:0]=00 Low drive capability - - 0.48 LSEDRV[1:0]=10 Medium low drive capability - - 0.75 LSEDRV[1:0]=01 Medium high drive capability - - 1.7 LSEDRV[1:0]=11 High drive capability - - 2.
PAGE 141
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.10 Electrical characteristics Internal clock source characteristics The parameters given in Table 46 and Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 18. High-speed internal (HSI) RC oscillator Table 46. HSI oscillator characteristics (1) Symbol fHSI Parameter Conditions Min Typ Max Unit Frequency - - 16 - MHz HSI user trimming step(2) - - - 1 % −8 - 4.
PAGE 142
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Low-speed internal (LSI) RC oscillator Table 47. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) Parameter Frequency Min Typ Max Unit 17 32 47 kHz (3) LSI oscillator startup time - 15 40 µs (3) LSI oscillator power consumption - 0.4 0.6 µA IDD(LSI) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by characterization results. 3. Guaranteed by design. Figure 34.
PAGE 143
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.11 Electrical characteristics PLL characteristics The parameters given in Table 48 and Table 49 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 18. Table 48. Main PLL characteristics Symbol Parameter Conditions Min Typ Max fPLL_IN PLL input clock(1) - 0.95(2) 1 2.
PAGE 144
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 49. PLLI2S characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.
PAGE 145
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 50. PLLISAI characteristics (continued) Symbol Parameter Min Typ Max VCO freq = 192 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 90 - - peak to peak - ±280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps FS clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLSAI)(4) PLLSAI power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.
PAGE 146
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ⁄ ( 4 × 10 ) ] = 250 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 – 1 ) × md × PLLN ) ⁄ ( 100 × 5 × MODEPER ) ] fVCO_OUT must be expressed in MHz.
PAGE 147
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 36. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [PG WPRGH 7LPH [WPRGH DL E 5.3.13 MIPI D-PHY characteristics The parameters given in Table 52 and Table 53 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 18. Table 52.
PAGE 148
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 52. MIPI D-PHY characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit VIL Output low level voltage - 1.1 1.2 1.
PAGE 149
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 53. MIPI D-PHY AC characteristics LP mode and HS/LP transitions(1) (continued) Symbol Parameter Conditions Min Typ Max TCLK-POST Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. - 62+52*UI - - TCLK-TRAIL Time that the transmitter drives the HS-0 state after the last payload clock bit of an HS transmission burst.
PAGE 150
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 37. MIPI D-PHY HS/LP clock lane transition timing diagram 7&/. 3267 7(27 9,/ &ORFN /DQH 7&/. 75$,/ 7+6 (;,7 7/3; 7&/. 35(3$5( 7&/. =(52 7&/. 35( 'DWD /DQH 7/3; 7+6 35(3$5( 9,/ 06 9 Figure 38. MIPI D-PHY HS/LP data lane transition timing diagram &ORFN /DQH 'DWD /DQH 7/3; 7+6 35(3$5( /3 /3 7+6 =(52 9,/ 75(27 /3 7(27 7+6 75$,/ 7+6 (;,7 06 9 5.3.
PAGE 151
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 54. DSI-PLL characteristics(1) (continued) Symbol IDD(PLL) Parameter PLL power consumption on VDD12 Conditions Min Typ Max fVCO_OUT = 500 MHz - 0.55 0.70 fVCO_OUT = 600 MHz - 0.65 0.80 fVCO_OUT = 1000 MHz - 0.95 1.20 Unit mA 1. Based on test during characterization. 5.3.
PAGE 152
Electrical characteristics 5.3.16 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 56. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.7 V - 14 - Write / Erase 16-bit mode, VDD = 2.1 V - 17 - Write / Erase 32-bit mode, VDD = 3.
PAGE 153
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 57. Flash memory programming (single bank configuration nDBANK=1) (continued) Symbol Vprog Parameter Programming voltage Min(1) Typ 32-bit program operation 2.7 - 3 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.7 - 3.6 V Conditions Max(1) Unit 1. Guaranteed by characterization results. 2. The maximum programming time is measured after 100K erase operations. Table 58.
PAGE 154
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 58. Flash memory programming (dual bank configuration nDBANK=0) (continued) Symbol Parameter tBE Bank erase time Vprog Programming voltage Min(1) Typ Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 32-bit program operation 2.7 - 3 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.
PAGE 155
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range. 5.3.17 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
PAGE 156
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.
PAGE 157
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 63. ESD absolute maximum ratings Symbol Ratings VESD(HBM) Electrostatic discharge voltage (human body model) VESD(CDM) Electrostatic discharge voltage (charge device model) Maximum Unit value(1) Conditions Class TA = +25 °C conforming to ANSI/ESDA/JEDEC JS-001-2012 2 2000 TA = +25 °C conforming to ANSI/ESD S5.3.12009, all packages except TFBGA100 3 250 TA = +25 °C conforming to ANSI/ESD S5.3.
PAGE 158
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 65.
PAGE 159
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 66.
PAGE 160
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 39.
PAGE 161
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 67. Output voltage characteristics Symbol Parameter Conditions Min Max CMOS port(2) IIO = +8 mA 2.7 V ≤VDD ≤3.6 V - 0.4 VDD − 0.4 - VDD − 0.4 - Output low level voltage for an I/O pin TTL port(2) IIO =+8mA 2.7 V ≤VDD ≤3.6 V - 0.4 VOH (3) Output high level voltage for an I/O pin except PC14 TTL port(2) IIO =-8mA 2.7 V ≤VDD ≤3.6 V 2.4 - VOL(1) Output low level voltage for an I/O pin IIO = +20 mA 2.
PAGE 162
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Unless otherwise specified, the parameters given in Table 68 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 18. Table 68.
PAGE 163
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 68. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Conditions Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD ≥ 2.7 V - - 100(4) CL = 30 pF, VDD ≥ 1.8 V - - 50 CL = 30 pF, VDD ≥ 1.7 V - - 42.5 CL = 10 pF, VDD≥ 2.
PAGE 164
Electrical characteristics 5.3.21 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 66: I/O static characteristics). Unless otherwise specified, the parameters given in Table 69 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 18. Table 69.
PAGE 165
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.22 Electrical characteristics TIM timer characteristics The parameters given in Table 70 are guaranteed by design. Refer to Section 5.3.20: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 70.
PAGE 166
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 72.
PAGE 167
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 72. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 µA IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.18.2: Internal reset OFF). 2.
PAGE 168
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 75. ADC static accuracy at fADC = 36 MHz Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Typ Max(1) ±4 ±7 ±2 ±3 ±3 ±6 ±2 ±3 ±3 ±6 fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA −VREF < 1.2 V Unit LSB 1. Guaranteed by characterization results. Table 76.
PAGE 169
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 42. ADC accuracy characteristics ; ,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3")$%!, 6 33! 6$$! AI C 1. See also Table 74. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5.
PAGE 170
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 44 or Figure 45, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 44.
PAGE 171
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.25 Electrical characteristics Temperature sensor characteristics Table 78. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - ±1 ±2 °C Average slope - 2.5 - mV/°C Voltage at 25 °C - 0.76 - V tSTART(2) Startup time - 6 10 µs TS_temp(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - µs TL(1) Avg_Slope (1) V25(1) 1.
PAGE 172
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 81. internal reference voltage (continued) Symbol Parameter TCoeff(2) tSTART (2) Conditions Min Typ Max Unit Temperature coefficient - - 30 50 ppm/°C Startup time - - 6 10 µs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Table 82. Internal reference voltage calibration values Symbol Parameter VREFIN_CAL 5.3.
PAGE 173
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 83. DAC characteristics (continued) Symbol IVREF+(4) Parameter DAC DC VREF current consumption in quiescent mode (Standby mode) Min Typ Max - 170 240 Unit µA Comments With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.
PAGE 174
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 83. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC measurement) - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. VDDA minimum value of 1.
PAGE 175
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 84. Minimum I2CCLK frequency in all I2C modes Symbol Parameter Condition Standard-mode Fast-mode f(I2CCLK) I2CCLK frequency Fast-mode Plus Min - 2 Analog filter ON DNF=0 8 Analog filter OFF DNF=1 9 Analog filter ON DNF=0 16 Analog filter OFF DNF=1 16 Unit MHz The SDA and SCL I/O requirements are met with the following restrictions: • The SDA and SCL I/O pins are not “true” open-drain.
PAGE 176
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx SPI interface characteristics Unless otherwise specified, the parameters given in Table 86 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.
PAGE 177
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 86. SPI dynamic characteristics(1) (continued) Symbol Conditions Min Typ Max Master mode 4 9(4) - - tsu(SI) Slave mode 4.5 - - th(MI) Master mode 3 0(4) - - Slave mode 2 - - tsu(MI) Parameter Data input setup time Data input hold time th(SI) ta(SO) Data output access time Slave mode 7 - 21 tdis(SO) Data output disable time Slave mode 5 - 12 Slave mode 2.7≤VDD≤3.6V - 6.
PAGE 178
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 48. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW WF 6&. WVX 166 WZ 6&.+ WD 62 WZ 6&./ WI 6&. WK 166 6&. LQSXW &3+$ &32/ &3+$ &32/ WY 62 WK 62 )LUVW ELW 287 0,62 RXWSXW WVX 6, WU 6&. 1H[W ELWV 287 WGLV 62 /DVW ELW 287 WK 6, 026, LQSXW )LUVW ELW ,1 1H[W ELWV ,1 /DVW ELW ,1 06Y 9 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 49.
PAGE 179
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics I2S interface characteristics Unless otherwise specified, the parameters given in Table 87 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.
PAGE 180
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 50. I2S slave timing diagram (Philips protocol)(1) &. ,QSXW WF &. &32/ &32/ WZ &.+ WK :6 WZ &./ :6 LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW WVX 6'B65 /6% UHFHLYH 6'UHFHLYH WK 6'B67 %LWQ WUDQVPLW /6% WUDQVPLW WK 6'B65 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH 06 9 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
PAGE 181
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics JATG/SWD characteristics Unless otherwise specified, the parameters given in Table 88 for JTAG/SWD are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 18, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C=30 pF • Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 5.3.
PAGE 182
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 89. Dynamics characteristics: SWD characteristics Symbol Parameter Fpp 1/tc(SWCLK) Conditions Min Typ Max 2.7V
PAGE 183
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 53. SWD timing diagram WF 6:&/. 6:&/. WVX 6:',2 WK 6:',2 WZ6:&/./ WZ 6:&/.
PAGE 184
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 90. SAI characteristics(1) (continued) Symbol tv(SD_B_ST) th(SD_B_MT) tv(SD_MT)_A th(SD_A_MT) Parameter Data output valid time Data output hold time Data output valid time Data output hold time Conditions Min Max Slave transmitter (after enable edge) 2.7≤VDD≤3.6V - 12 Slave transmitter (after enable edge) 1.71≤VDD≤3.
PAGE 185
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 55. SAI slave timing waveforms F3#+ 3!)?3#+?8 TW #+(?8 3!)?&3?8 INPUT TW #+,?8 TH &3 TSU &3 TH 3$?34 TV 3$?34 3!)?3$?8 TRANSMIT 3LOT N 3LOT N TSU 3$?32 TH 3$?32 3!)?3$?8 RECEIVE 3LOT N -3 6 USB OTG full speed (FS) characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 91.
PAGE 186
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 92. USB OTG full speed DC electrical characteristics (continued) Symbol Parameter PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) RPD Max. (1) Typ. 17 21 24 2.4 5.2 8 (1) Unit VIN = VDD PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) RPU Min. Conditions kΩ PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.55 0.95 1.35 2.1 1.
PAGE 187
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver.
PAGE 188
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 57. ULPI timing diagram #LOCK #ONTROL )N 5,0)?$)2 5,0)?.84 T3# T(# T3$ T($ DATA )N BIT T$# T$# #ONTROL OUT 5,0)?340 T$$ DATA OUT BIT AI C Table 96. Dynamic characteristics: USB ULPI(1) Symbol Parameter Conditions Min. Typ. Max. tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 2 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 1.
PAGE 189
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 58. Ethernet SMI timing diagram W0'& (7+B0'& WG 0',2 (7+B0',2 2 WVX 0',2 WK 0',2 (7+B0',2 , 06 9 Table 97. Dynamics characteristics: Ethernet MAC signals for SMI(1) Symbol tMDC Parameter MDC cycle time(2.38 MHz) Min Typ Max 400 400 403 Td(MDIO) Write data valid time THCLK + 1 tsu(MDIO) Read data setup time 12.5 - - th(MDIO) Read data hold time 0 - - Unit THCLK + 1.5 THCLK + 3 ns 1.
PAGE 190
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 98. Dynamics characteristics: Ethernet MAC signals for RMII(1) Symbol Parameter Min Typ Max tsu(RXD) Receive data setup time 1 - - tih(RXD) Receive data hold time 2 - - tsu(CRS) Carrier sense setup time 2 - - tih(CRS) Carrier sense hold time 2 - - td(TXEN) Transmit enable valid delay time 7.5 8 12 td(TXD) Transmit data valid delay time 7 7.5 12.5 Unit ns 1.
PAGE 191
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics 1. Guaranteed by characterization results. Table 100. MDIO Slave timing parameters Symbol Min Typ Max Unit Management Data clock - - 40 MHz td(MDIO) Management Data input/output output valid time 7 8 20 tsu(MDIO) Management Data input/output setup time 4 - - th(MDIO) Management Data input/output hold time 1 - - FsDC Parameter ns The MDIO controller is mapped on APB2 domain.
PAGE 192
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Refer to Section 5.3.20: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 62 through Figure 65 represent asynchronous waveforms and Table 101 through Table 108 provide the corresponding timings.
PAGE 193
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 101. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Min Max 2THCLK − 1 2 THCLK +1 0 0.5 2THCLK − 1 2THCLK + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.
PAGE 194
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms TW .% &-#?.%X &-#?./% TV .7%?.% TW .7% T H .%?.7% &-#?.7% TV !?.% &-#?!; = TH !?.7% !DDRESS TV ",?.% &-#?.",; = TH ",?.7% .", TV $ATA?.% TH $ATA?.7% $ATA &-#?$; = T V .!$6?.% &-#?.!$6 TW .!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 103.
PAGE 195
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 104. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) Min Max Unit 8THCLK − 1 8THCLK + 1 6THCLK − 1.5 6THCLK + 0.5 FMC_NWE low time tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK − 1 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK + 2 - ns 1. Guaranteed by characterization results. Figure 64.
PAGE 196
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 105. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Min Max 3THCLK − 1 3THCLK + 1 2THCLK 2THCLK + 0.5 THCLK − 1 THCLK + 1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time THCLK − 0.5 THCLK+1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) THCLK + 0.
PAGE 197
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 65. Asynchronous multiplexed PSRAM/NOR write waveforms TW .% &-#? .%X &-#?./% TV .7%?.% TW .7% T H .%?.7% &-#?.7% TH !?.7% TV !?.% &-#? !; = !DDRESS TV ",?.% TH ",?.7% &-#? .",; = .", T V !?.% &-#? !$; = T V $ATA?.!$6 !DDRESS TH $ATA?.7% $ATA TH !$?.!$6 T V .!$6?.% TW .!$6 &-#?.!$6 &-#?.7!)4 TH .%?.7!)4 TSU .7!)4?.% -3 6 Table 107.
PAGE 198
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1. Guaranteed by characterization results. Table 108. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol tw(NE) tw(NWE) Parameter FMC_NE low time FMC_NWE low time Min Max 9THCLK – 1 9THCLK + 1 Unit 7THCLK – 0.5 7THCLK + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6THCLK + 2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK – 1 - 1. Guaranteed by characterization results.
PAGE 199
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 66. Synchronous multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &-#?#,+ $ATA LATENCY TD #,+, .%X, &-#?.%X T D #,+, .!$6, TD #,+( .%X( TD #,+, .!$6( &-#?.!$6 TD #,+, !6 TD #,+( !)6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% T D #,+, !$6 &-#?!$; = TD #,+, !$)6 TSU !$6 #,+( !$; = TH #,+( !$6 TSU !$6 #,+( $ TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B &-#?.
PAGE 200
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 109. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Min Max 2THCLK − 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1. td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK − 0.5 - tw(CLK) td(CLKL-NExL) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..
PAGE 201
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 67. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+( .%X( &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+( .7%( TD #,+, .7%, &-#?.7% TD #,+, !$)6 TD #,+, !$6 &-#?!$; = TD #,+, $ATA TD #,+, $ATA !$; = $ $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+( .",( &-#?.
PAGE 202
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 110. Synchronous multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK − 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2 .5 THCLK - - 1.5 THCLK + 0.5 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
PAGE 203
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 68. Synchronous non-multiplexed NOR/PSRAM read timings TW #,+ TW #,+ &-#?#,+ TD #,+, .%X, TD #,+( .%X( $ATA LATENCY &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+, ./%, TD #,+( ./%( &-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( &-#?$; = TH #,+( $6 $ TSU .7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B $ TH #,+( .7!)46 TSU .7!)46 #,+( &-#?.
PAGE 204
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 1. Guaranteed by characterization results. Figure 69. Synchronous non-multiplexed PSRAM write timings TW #,+ TW #,+ &-#?#,+ TD #,+, .%X, TD #,+( .%X( $ATA LATENCY &-#?.%X TD #,+, .!$6, TD #,+, .!$6( &-#?.!$6 TD #,+( !)6 TD #,+, !6 &-#?!; = TD #,+, .7%, TD #,+( .7%( &-#?.7% TD #,+, $ATA TD #,+, $ATA $ &-#?$; = $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TD #,+( .",( TH #,+( .7!)46 &-#?.
PAGE 205
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 112. Synchronous non-multiplexed PSRAM write timings(1) Symbol Min Max 2THCLK − 0.5 - - 2 THCLK + 0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 2.5 THCLK - - 1.5 THCLK + 1 - t(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..
PAGE 206
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 70. NAND controller waveforms for read access &-#?.#%X !,% &-#?! #,% &-#?! &-#?.7% TD !,% ./% TH ./% !,% &-#?./% .2% TSU $ ./% TH ./% $ &-#?$; = -3 6 Figure 71. NAND controller waveforms for write access &-#?.#%X !,% &-#?! #,% &-#?! TH .7% !,% TD !,% .7% &-#?.7% &-#?./% .2% TV .7% $ TH .7% $ &-#?$; = -3 6 206/255 Downloaded from Arrow.com.
PAGE 207
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 72. NAND controller waveforms for common memory read access &-#?.#%X !,% &-#?! #,% &-#?! TH ./% !,% TD !,% ./% &-#?.7% TW ./% &-#?./% TSU $ ./% TH ./% $ &-#?$; = -3 6 Figure 73. NAND controller waveforms for common memory write access &-#?.#%X !,% &-#?! #,% &-#?! TD !,% ./% TW .7% TH ./% !,% &-#?.7% &-#?. /% TD $ .7% TV .7% $ TH .7% $ &-#?$; = -3 6 Table 113.
PAGE 208
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 114. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter Min Max Unit 4THCLK − 0.5 4THCLK + 0.
PAGE 209
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 115. SDRAM read timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5 tsu(SDCLKH _Data) Data input setup time 1.5 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 3.5 td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0.
PAGE 210
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 75. SDRAM write access waveforms &-#?3$#,+ TD 3$#,+,?!DD# TH 3$#,+,?!DD2 TD 3$#,+,?!DD2 &-#?!> @ 2OW N #OL #OL #OLI #OLN TH 3$#,+,?!DD# TH 3$#,+,?3.$% TD 3$#,+,?3.$% &-#?3$.%; = TH 3$#,+,?.2!3 TD 3$#,+,?.2!3 &-#?3$.2!3 TD 3$#,+,?.#!3 TH 3$#,+,?.#!3 TD 3$#,+,?.7% TH 3$#,+,?.7% &-#?3$.#!3 &-#?3$.7% TD 3$#,+,?$ATA $ATA &-#?$; = $ATA $ATAI $ATAN TH 3$#,+,?$ATA TD 3$#,+,?.", &-#?.
PAGE 211
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 118. LPSDR SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2THCLK − 0.5 2THCLK + 0.5 td(SDCLKL _Data) Data output valid time - 2.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL-SDNWE) SDNWE valid time - 2.5 th(SDCLKL-SDNWE) SDNWE hold time 0 - td(SDCLKL- SDNE) Chip select valid time - 0.
PAGE 212
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 119. Quad-SPI characteristics (continued)in SDR mode(1) (continued) Symbol Parameter Conditions Min Typ Max tw(CKH) tw(CKL) Quad-SPI clock high and low time - t(CK)/2 - 1 - t(CK)/2 t(CK)/2 - t(CK)/2 + 1 ts(IN) Data input setup time 0.5 - - th(IN) Data input hold time 3 - - tv(OUT) Data output valid time 2.7 V
PAGE 213
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 76. Quad-SPI timing diagram - SDR mode WU &. W &. &ORFN WZ &.+ WY 287 WZ &./ WI &. WK 287 'DWD RXWSXW ' ' WV ,1 'DWD LQSXW ' ' WK ,1 ' ' 06Y 9 Figure 77. Quad-SPI timing diagram - DDR mode WU &. &ORFN W &. WYI 287 'DWD RXWSXW WZ &.+ WKU 287 ' WYU 287 ' ' WZ &./ WKI 287 ' WVI ,1 WKI ,1 'DWD LQSXW ' ' WI &. ' ' WVU ,1 WKU ,1 ' ' ' ' 06Y 9 5.3.
PAGE 214
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 78. DCMI timing diagram '&0,B3,;&/. '&0,B3,;&/. WK +6<1& WVX +6<1& '&0,B+6<1& WK +6<1& WVX 96<1& '&0,B96<1& WVX '$7$ WK '$7$ '$7$> @ 06 9 5.3.
PAGE 215
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Figure 79. LCD-TFT horizontal timing diagram W&/. /&'B&/. /&'B96<1& WY +6<1& WY +6<1& /&'B+6<1& WK '( WY '( /&'B'( WY '$7$ /&'B5> @ /&'B*> @ /&'B%> @ 1JYFM 1JYFM 1JYFM / WK '$7$ +6<1& +RUL]RQWDO ZLGWK EDFN SRUFK $FWLYH ZLGWK +RUL]RQWDO EDFN SRUFK 2QH OLQH 06 9 Figure 80. LCD-TFT vertical timing diagram W&/. /&'B&/.
PAGE 216
Electrical characteristics 5.3.34 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Digital filter for Sigma-Delta Modulators (DFSDM) characteristics Unless otherwise specified, the parameters given in Table 123 for DFSDM are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage summarized in Table 18, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30pF • Measurement points are done at CMOS levels: 0.
PAGE 217
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Electrical characteristics Table 123. DFSDM measured timing 1.71-3.6V (continued) Symbol Parameter Conditions Min Typ Max twh(CKIN) twl(CKIN) Input clock high and low time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.6 V TCKIN/2 - 0.5 TCKIN/2 - tsu Data input setup time SPI mode (SITP[1:0]=0,1), External clock mode (SPICKSEL[1:0]=0), 1.71 < VDD < 3.
PAGE 218
Electrical characteristics 5.3.35 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx DFSDM timing diagrams ')6'0B&.,1\ ')6'0B'$7,1\ ')6'0B&.287 63,&.6(/ WVX WK WZO WZK WU WI WU WI 6,73 WVX WK 6,73 63,&.6(/ 63,&.6(/ 63,&.6(/ WVX ')6'0B'$7,1\ 63, WLPLQJ 63,&.6(/ 63, WLPLQJ 63,&.6(/ Figure 81. Channel transceiver timing diagrams WK WZO WZK 6,73 WVX WK 6,73 ')6'0B'$7,1\ 0DQFKHVWHU WLPLQJ 6,73 6,73 UHFRYHUHG FORFN UHFRYHUHG GDW
PAGE 219
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 5.3.
PAGE 220
Electrical characteristics STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 124. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50 MHz 8.5 9.
PAGE 221
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 LQFP100 14x 14 mm, low-profile quad flat package information Figure 84.
PAGE 222
Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 126. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.
PAGE 223
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Figure 85. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint AI C 1. Dimensions are expressed in millimeters. DocID029041 Rev 6 223/255 254 Downloaded from Arrow.com.
PAGE 224
Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP100 device making The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 86. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example 3URGXFW LGHQWLILFDWLRQ 45.
PAGE 225
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6.2 Package information TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information GGG & Figure 87. TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array package outline 6($7,1* 3/$1( % $ EDOO LQGH[ $ EDOO DUHD LGHQWLILHU ' H $ $ $ & ' ) ( ( * $ % & ' ( ) * + . H $ %27720 9,(: E %$//6 HHH & $ % III & 723 9,(: $ 4B0(B9 1. Drawing is not to scale. Table 127.
PAGE 226
Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 127. TFBGA100, 8 x 8 × 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D 7.850 8.000 8.150 0.3091 0.3150 0.3209 D1 - 7.200 - - 0.2835 - E 7.850 8.000 8.150 0.3091 0.3150 0.3209 E1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - F - 0.400 - - 0.0157 - G - 0.400 - - 0.0157 - ddd - - 0.100 - - 0.
PAGE 227
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 128. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA) Dimension Recommended values Pitch 0.8 Dpad 0.400 mm Dsm 0.470 mm typ (depends on the soldermask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm TFBGA100 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location.
PAGE 228
Package information 6.3 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP144 20 x 20 mm, low-profile quad flat package information Figure 90. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # $ , $ + ! '!5'% 0,!.% , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. 228/255 Downloaded from Arrow.com.
PAGE 229
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 129. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.
PAGE 230
Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 91. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint DL H 1. Dimensions are expressed in millimeters. 230/255 Downloaded from Arrow.com.
PAGE 231
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information LQFP144 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 92. LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 3 45.
PAGE 232
Package information 6.4 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP176 24 x 24 mm, low-profile quad flat package information Figure 93. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline C ! ! ! # 3EATING PLANE MM GAUGE PLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. 232/255 Downloaded from Arrow.com.
PAGE 233
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 130. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 - 1.450 0.0531 - 0.0060 b 0.170 - 0.270 0.0067 - 0.0106 C 0.090 - 0.200 0.0035 - 0.0079 D 23.900 - 24.100 0.9409 - 0.9488 E 23.900 - 24.100 0.9409 - 0.9488 e - 0.500 - - 0.
PAGE 234
Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 94. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters. 234/255 Downloaded from Arrow.com.
PAGE 235
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information LQFP176 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package top view example 3URGXFW LGHQWLILFDWLRQ 45.
PAGE 236
Package information 6.5 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx LQFP208 28 x 28 mm low-profile quad flat package information Figure 96. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & FFF & PP $ *$8*( 3/$1( . / ' / ' ' 3,1 ,'(17,),&$7,21 ( ( ( E H 6)@.&@7 1. Drawing is not to scale. 236/255 Downloaded from Arrow.com.
PAGE 237
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 131. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 -- - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 29.800 30.000 30.200 1.1732 1.1811 1.1890 D1 27.800 28.000 28.200 1.0945 1.
PAGE 238
Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 97. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package recommended footprint -3 6 1. Dimensions are expressed in millimeters. 238/255 Downloaded from Arrow.com.
PAGE 239
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information LQFP208 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 98. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package top view example 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 45. ' #*5 3LQ LGHQWLILHU 'DWH FRGH \HDU ZHH
PAGE 240
Package information 6.6 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx WLCSP 180-bump, 5.5 x 6 mm, wafer level chip scale package information Figure 99. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package outline H ' ) $ %$// /2&$7,21 * '(7$,/ $ H ( $ 25,(17$7,21 5()(5(1&( H $ H 723 9,(: $ $ %27720 9,(: 6,'( 9,(: %803 6($7,1* 3/$1( '(7$,/ $ 527$7(' R $ *B:/&63 B0(B9 1. Drawing is not to scale. 240/255 Downloaded from Arrow.com.
PAGE 241
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Table 132. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - A3 - 0.025 - - 0.0010 - (2) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 5.502 5.537 5.572 0.2166 0.2180 0.2194 E 6.060 6.095 6.130 0.2386 0.2400 0.
PAGE 242
Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Figure 100. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package recommended footprint 'SDG 'VP $ *B:/&63 B)3B9 1. Dimensions are expressed in millimeters. Table 133. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules (0.4 mm pitch) 242/255 Downloaded from Arrow.com. Dimension Recommended values Pitch 0.4 Dpad 0.225 mm Dsm 0.290 mm typ.
PAGE 243
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information WLCSP180 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 101. WLCSP180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package top view example 3URGXFW LGHQWLILFDWLRQ 45.
PAGE 244
Package information 6.7 STM32F765xx STM32F767xx STM32F768Ax STM32F769xx UFBGA176+25, 10 x 10, 0.65 mm ultra thin fine-pitch ball grid array package information Figure 102. UFBGA176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array package outline & ^ĞĂƚŝŶŐ ƉůĂŶĞ Ϯ ϰ ĚĚĚ ϭ ď $ EDOO LGHQWLILHU Ğ $ EDOO LQGH[ DUHD $ & & Ğ Z ϭϱ ϭ KddKD s/ t E EDOOV dKW s/ t HHH 0 & $ III 0 & Ϭ ϳͺD ͺsϲ 1. Drawing is not to scale. Table 134.
PAGE 245
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information Figure 103. UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint 'SDG 'VP Ϭ ϳͺ&Wͺsϭ Table 135. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.
PAGE 246
Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx UFBGA 176+25 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 104. UFBGA 176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array package top view example 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) ,,.
PAGE 247
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 6.8 Package information TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package information Figure 105. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ ' H ; $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ' $ * ( ( H < 5 E EDOOV HHH 0 = < ; III 0 = %27720 9,(: 723 9,(: $ / B0(B9 1. Drawing is not to scale. Table 136. TFBGA216, 13 × 13 × 0.
PAGE 248
Package information STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 136. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max G - 0.900 - - 0.0354 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 106. TFBGA216, 13 x 13 mm, 0.
PAGE 249
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Package information TFBGA216 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 107. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array package top view example 3URGXFW LGHQWLILFDWLRQ 45.
PAGE 250
Package information 6.
PAGE 251
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx 7 Ordering information Ordering information Table 139.
PAGE 252
Recommendations when using internal reset OFF Appendix A STM32F765xx STM32F767xx STM32F768Ax Recommendations when using internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.
PAGE 253
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Revision history Revision history Table 141. Document revision history Date Revision 21-Mar-2016 1 Initial release. 2 DFSDM replaced by DFSDM1 in: – Table 11: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions. – Table 13: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping. – Table 14: STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses. – Section 5.3.
PAGE 254
Revision history STM32F765xx STM32F767xx STM32F768Ax STM32F769xx Table 141. Document revision history (continued) Date 09-Aug-2017 11-Sep-2017 254/255 Downloaded from Arrow.com. Revision Changes 5 Updated note 1 below all the package device marking figures. Updated cover title. Updated Section 1: Description. Updated Section 2.47: DSI Host (DSIHOST) video mode interface features. Added Table 9: DFSDM implementation. Updated Figure 11: STM32F76xxx LQFP100 pinout pin 43 and pin 44.
PAGE 255
STM32F765xx STM32F767xx STM32F768Ax STM32F769xx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.