Datasheet
Pinouts and pin description STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
84/255 DocID029041 Rev 6
---J7-- - ---- VSS S-- - -
---J8-- - ---- VSS S-- - -
---J9-- - ---- VSS S-- - -
---J10-- - ---- VSS S-- - -
---K6--- ---- VSS S-- - -
---K7--- ---- VSS S-- - -
---K8--- ---- VSS S-- - -
---K9--- ---- VSS S-- - -
---K10-- - ---- VSS S-- - -
1. NC (not-connected) pins are not bonded. They must be configured by software to output push-pull and forced to 0 in the
output data register to avoid an extra current consumption in low-power modes. list of pins: PI8, PI12, PI13, PI14, PF6,
PF7, PF8, PF9, PC2, PC3, PC4, PC5, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PH6, PH7, PJ12, PJ13, PJ14, PJ15, PG14,
PK3, PK4, PK5, PK6 and PK7.
2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os
must not be used as a current source (e.g. to drive an LED).
3. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
4. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low).
5. Internally connected to VDD or VSS depending on part number.
Table 11. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx pin and
ball definitions (continued)
Pin Number
Pin name (function after reset
Pin type
I/O structure
Notes
Alternate functions
Additional
functions
STM32F765xx
STM32F767xx
STM32F768Ax
STM32F769xx
TFBGA100
LQFP100
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
WLCSP180
(1)
LQFP176
LQFP208
TFBGA216
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